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2019-01-29arm: stm32mp1: deploy spl in root folderPatrick Delaunay
Update generation of spl binaries - continue to generate all SPL files in spl sub-directory - copy in root folder the needed file for user (YOCTO, buildroot): u-boot-spl.stm32 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-01-26linker: Modify linker scripts to be more genericTom Rini
Make use of "IMAGE_MAX_SIZE" and "IMAGE_TEXT_BASE" rather than CONFIG_SPL_MAX_SIZE and CONFIG_SPL_TEXT_BASE. This lets us re-use the same script for both SPL and TPL. Add logic to scripts/Makefile.spl to pass in the right value when preprocessing the script. Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Jagan Teki <jagan@openedev.com> Cc: Maxime Ripard <maxime.ripard@bootlin.com> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: York Sun <york.sun@nxp.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Heiko Schocher <hs@denx.de> Cc: Adam Ford <aford173@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Tested-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Tested-by: Adam Ford <aford173@gmail.com> #da850evm & omap3_logic_somlv Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-01-26rockchip: Add TPL_MAX_SIZE for RK3288Tom Rini
Per Kever Yang, 32768 is a reasonable max size for TPL on RK3288. Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-01-26PowerPC: Stop re-using CONFIG_SPL_TEXT_BASE for TPLTom Rini
Rather than checking for CONFIG_TPL_BUILD and then re-defining CONFIG_SPL_TEXT_BASE make use of CONFIG_TPL_TEXT_BASE directly. Cc: York Sun <york.sun@nxp.com> Cc: Po Liu <po.liu@nxp.com> Cc: Qiang Zhao <qiang.zhao@nxp.com> Cc: Timur Tabi <timur@tabi.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2019-01-26Merge branch '2019-01-25-master-imports'Tom Rini
- snapdragon 820c improvements - poplar updates - DFU + SPL cleanups - Improve the mediatek mmc driver - Other minor cleanups / improvements
2019-01-26ARM: mach-omap2: Kconfig: Allow OMAP5 devices to set entry pointAndrew F. Davis
Like AM33xx and AM43xx, DRA7xx and AM57xx devices may need to have an non-standard boot address in memory. This may be due to the device being a high security variant, which place the Initial SoftWare (ISW) after certificates and secure software. Allow these devices to set this from Kconfig. Signed-off-by: Andrew F. Davis <afd@ti.com>
2019-01-26spl: Kconfig: Drop the _SUPPORT postfix from SPL_DFUAndrew F. Davis
The symbol CONFIG_SPL_DFU_SUPPORT in SPL build has the same meaning as CONFIG_DFU in regular U-Boot. Drop the _SUPPORT to allow for cleaner use in code. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Lukasz Majewski <lukma@denx.de>
2019-01-26arm64: dt: poplar: add optee nodeIgor Opaniuk
As Poplar supports running TF-A with OP-TEE as BL32 payload, add op-tee node in DT, which enables usage of OP-TEE driver (which provides an interface for requesting services from OP-TEE). Signed-off-by: Igor Opaniuk <igor.opaniuk@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-25poplar: clean up board level mmc initialization codeShawn Guo
We have converted mmc to driver model on Poplar. So let's clean up board level mmc initialization code. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2019-01-25poplar: sync up device tree with kernel 4.20Shawn Guo
It adds missing pinctrl headers, updates clock header and sync up Poplar device tree with kernel 4.20 release. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2019-01-25dts: 820c: Add pinctrl node and uart muxRamon Fried
* Add pinctrl node for TLMM and add mux request for uart node. * Rename uart to the actual board uart port. * Fix indentendation of sdhc2 node. Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2019-01-25arm: mach-snapdragon: pinctrl: clarify gpio disable bitRamon Fried
The TLMM_GPIO_ENABLE bit is actually use to disable the GPIO. change it to TLMM_GPIO_DISABLE so it's clearer. Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2019-01-25arm: mach-snapdragon: add pinctrl driver for db820cRamon Fried
Add pinctrl driver for Dragonboard820c, currently with only one mux func to initialize pins for serial console. Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2019-01-25arm: mach-snapdragon: db820c: Actually init PLL for serialRamon Fried
The PLL for the UART was not set, and relied on previous initializtion made by LK. add the appropriate initialization. Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2019-01-25arm: stm32mp1: deploy spl in root folderSean Nyekjær
Deploy u-boot-spl.stm32 binary in u-boot root folder like the rest of the boards. This makes it more streamlined when building in Yocto, Buildroot etc.. Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
2019-01-25Merge tag 'arc-fixes-for-2019.04-rc1' of git://git.denx.de/u-boot-arcTom Rini
A couple of trivial fixes and improvements for ARC Most notable are: * Move of ENV_SIZE/ENV_OFFSET to Kconfig * Fix with private structure allocation for arc_uart * Definition of CONFIG_SYS_CACHELINE_SIZE useful for building drivers
2019-01-25ARC: cache: define CONFIG_SYS_CACHELINE_SIZE as ARCH_DMA_MINALIGNAlexey Brodkin
Even though we don't use CONFIG_SYS_CACHELINE_SIZE in ARC-specific code it is used a lot in different drivers for alignment purposes. So we define it and make much more drivers at least compilable for ARC. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2019-01-25ARC: Fix iteration in arc_xx_version()Alexey Brodkin
"i" gets incremented before we're entering loop body and effectively we iterate from 1 to 8 instead of 0 to 7. This way we: a) Skip the first line of struct hs_versions b) Go over it and access memory beyond the structure Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2019-01-24Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini
2019-01-24Merge tag 'mpc85xx-for-v2019.04-rc1' of git://git.denx.de/u-boot-mpc85xxTom Rini
mpc85xx config.mk: Add support for -msingle-pic-base
2019-01-24ARM: zynq: Remove unused GEM addressesMichal Simek
With DM in place there is no need to have GEM addresses in headers. None is using them. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24arm64: zynqmp: Remove unused GEM addressesMichal Simek
With DM in place there is no need to have GEM addresses in headers. None is using them. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24zynq: Kconfig: extend the bootstrap malloc() poolAnton Gerasimov
Most of the memory is being consumed by device binding code, more space needed for other data structures. Z-turn board has already hit the limit, others may follow soon. Measuring only the memory consumed in device_bind_common, I've got the following results (in decimal): root_driver: 108 mod_exp_sw: 108 amba: 120 serial@e0000000 aka uart0: 112 serial@e0001000 aka uart1: 88 spi@e000d000 aka qspi: 120 sdhci@e0100000 aka mmc0: 455 sdhci@e0100000.blk: 208 slcr@f8000000: 96 clkc@100: 72 (total) 1487 = 0x5cf of 0x600 Signed-off-by: Anton Gerasimov <tossel@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24topic-miamiplus: Run CPU at 800MHz for speedgrade-2Mike Looijmans
The miamiplus contains a speedgrade-2 device, which may run the CPU at 800MHz. Change the PLL setting to 800MHz, and adapt the setpoints in the devicetree. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24arm64: zynqmp: Move SoC sources to mach-zynqmpMichal Simek
Similar changes was done for Zynq in past and this patch just follow this pattern to separate cpu code from SoC code. Move arch/arm/cpu/armv8/zynqmp/* -> arch/arm/mach-zynqmp/* And also fix references to these files. Based on "ARM: zynq: move SoC sources to mach-zynq" (sha1: 0107f2403669f764ab726d0d404e35bb9447bbcc) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24arm64: zynqmp: Setup proper SPI dependencyMichal Simek
Select DM_SPI/DM_SPI_FLASH for the whole SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24ARM: zynqmp_r5: Setup DM_ETH/MMC if NET/MMC is enabledMichal Simek
Setup proper ETH/MMC dependency for the whole platform. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24arm64: zynqmp: Setup DM_ETH/MMC if NET/MMC is enabledMichal Simek
Setup proper ETH/MMC dependency for the whole platform. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24arm64: versal: Setup DM_ETH/MMC if NET/MMC is enabledMichal Simek
Setup proper ETH/MMC dependency for the whole platform. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24arm64: zynqmp: Fix mmc node names to be in sync with kernelSiva Durga Prasad Paladugu
This patches renames sd nodes in dts to be in line with kernel. This patch also modifies the references for the same in code. It checks mmc first to have no time penalty for new DT node names based on left-to-right expression evaluation. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24arm64: zynqmp: Do not protect zynqmp_pmufw_version()Michal Simek
There is hard dependency for CLK_ZYNQMP to have zynqmp_pmufw_version() but also FPGA code is calling this function which is possible to use without actual CLK_ZYNQMP firmware driver to be enabled. This patch enables the case where only fixed-clock CLK setup is used. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-23mpc85xx: Add support for -msingle-pic-baseJoakim Tjernlund
-msingle-pic-base is a new gcc(from 4.6) option for ppc and it reduces the size of my u-boot with about 4-5 KB. While at it, add -fno-jump-tables too to save a few more bytes. e5500 core: size u-boot.bef text data bss dec hex filename 473043 23772 307104 803919 c444f u-boot.bef size u-boot.aft text data bss dec hex filename 453195 23772 307104 784071 bf6c7 u-boot.aft e500 core: size u-boot.bef text data bss dec hex filename 292998 17868 24968 335834 51fda u-boot.bef size u-boot.aft text data bss dec hex filename 288002 17868 24968 330838 50c56 u-boot.aft Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com> Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-23MSCC: Add board support for Serval SoC family.Horatiu Vultur
Add board support and configuration for Jaguar2 SoC family. The detection of the board type is based on the phy ids. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-23MSCC: Add device tree for Serval pcb106 boardHoratiu Vultur
Add device tree based on evaluation board pcb106. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-01-23MSCC: add device tree for Serval pcb105 boardHoratiu Vultur
Add device tree based on evaluation board pcb105. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-01-23MSCC: Add support for Serval SoC family.Horatiu Vultur
As Ocelot, Servalt, Luton and Jaguar2, this family of SoCs are found in Microsemi Switches solution. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-23MSCC: Add board support for Servalt SoC familyHoratiu Vultur
Add board support, configuration and DTS for Servalt SoC family. Currently there is one board in this family. Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-01-23MSCC: Add support for Servalt SoC family.Horatiu Vultur
As Ocelot, Luton and Jaguar2, this family of SoCs are found in Microsemi Switches solution. Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-01-23MIPS: mscc: ocelot: Add ethernet nodes for OcelotGregory CLEMENT
Import Ethernet related nodes from Linux Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-01-22nds32: dts: Fix mmc node compatible stringRick Chen
In the two commits: cf3922dddc44a968685b535f2af195f1e51f4a7b mmc: ftsdc010_mci: Sync compatible with DT mmc node c14e90e8445e7b1c3531b4bdeb778c47bd6570eb riscv: dts: Sync DT with Linux Kernel ftsdc010_mci's compatible has been modified as "andestech,atfsdc010" for RISC-V synchronization. But ae3xx.dts and ag101p.dts which are used for nds32 adp-ae3xx and adp-ag101p platforms did not be modified correctly at that time. It will cause mmc detection failure. Fix it here. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
2019-01-22nds32: Fix boot fail issue when build with elf-mculib.Rick Chen
Add -mcmodel=large can let elf-mculib have the same default behavior just like linux-glibc. And it help to pass U-Boot booting sequence. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
2019-01-22nds32: Generate SW fpu instruction.Rick Chen
Force it to generate SW fup instruction. It help to avoid bugs when running on no-HW-fpu board, but compile with v3f which support HW fpu instruction. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
2019-01-22nds32: Remove gcc unused optionRick Chen
-G0 is an old option, not support now, So remove it. It can help to fix compile error when build with nds32 pre-build toolchain. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
2019-01-21Merge git://git.denx.de/u-boot-marvellTom Rini
- Sync Armada-38x dts with Linux 4.20 from Chris - Misc changes and enhancements to Turris Mox (v4) from Marek - Reserve PSCI area for Armada 8k from Heinrich - New Allied Telesis x530 board (Armada-385) from Chris - Misc minor changes (defconfig etc)
2019-01-21ARM: mvebu: add support for Allied Telesis x530Chris Packham
This is a range of stackable network switches. The SoC is Armada-385 and there are a number of variants with differing network port configurations. The DP variants are intended for a harsher operating environment so they use a different i2c mux and fit industrial-temp parts. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2019-01-21arm64: dts: marvell: armada-ap806: reserve PSCI areaHeinrich Schuchardt
The memory area [0x4000000-0x4200000[ is occupied by the PSCI firmware. Any attempt to access it from U-Boot leads to an immediate crash. So let's make the same memory reservation as the vendor device tree. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2019-01-21arm: mvebu: turris_mox: Support 1 GB version of Turris MoxMarek Behún
Use get_ram_size to determine if the RAM size on Turris Mox is 512 MiB or 1 GiB. Signed-off-by: Marek Behún <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
2019-01-21arm: mvebu: dts: Fix Turris Mox device treeMarek Behún
DTC issues a warning because #address-cells and #size-cells properties are not set in the mdio node. Also add ethernet1 alias. Also add RTC node. Also fix USB3 regulator startup delay time. Also fix PCI Express SERDES speed to 5 GHz (this is only cosmetic, the speed value is not used byt the comphy driver for PCI Express, but should be 5 GHz nonetheless). Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2019-01-21arm: mvebu: turris_mox: Check and configure modulesMarek Behún
Check if Mox modules are connected in supported mode, then configure the MDIO addresses of switch modules. Signed-off-by: Marek Behún <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
2019-01-21ARM: mvebu: sync Armada-38x dts with Linux 4.20Chris Packham
Sync the Armada-38x device tree files with Linux 4.20-rc5. The changes not taken are new compatible strings for the uart and nand flash controller. The nand binding is best updated if/when the mtd/nand infrastructure is updated. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
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