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2016-11-23powerpc: P1020MBG: Separate from P1_P2_RDB_PC in KconfigYork Sun
Use TARGET_P1020MBG instead of sharing with TARGET_P1_P2_RDB_PC to simplify Kconfig and other macros. Remove macro CONFIG_P1020MBG. Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23powerpc: P1017: Drop configuration for P1017York Sun
P1017 is a single-core version of P1023. There is no P1017 target configured. Drop related macros. P1017 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23powerpc: P1014: Drop configuration for P1014York Sun
P1014 is a variant of P1010. There is no P1014 target configured. Drop related macros. P1014 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23powerpc: P1013: Drop configuration for P1013York Sun
P1013 is a single-core version of P1022. There is no P1022 target configured. Drop related macros. P1022 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23powerpc: P1012: Drop configuration for P1012York Sun
P1012 is a single-core version of P1021. There is no P1012 target configured. Drop related macros. P1012 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23powerpc: P1011: Remove macro CONFIG_P1011York Sun
Replace CONFIG_P1011 with ARCH_P1011 in Kconfig. P1011RDB seems to be in scrapyard though. Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23powerpc: P1023: Remove macro CONFIG_P1023York Sun
Replace CONFIG_P1023 with ARCH_P1023 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23powerpc: P1022: Remove macro CONFIG_P1022York Sun
Replace CONFIG_P1022 with ARCH_P1022 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23powerpc: P1010RDB: Remove macros CONFIG_P1010RDB_PA and CONFIG_P1010RDB_PBYork Sun
Remove CONFIG_P1010RDB_PA and CONFIG_P1010RDB_PB and split TARGET_P1010RDB to TARGET_P1010RDB_PA and TARGET_P1010RDB_PB in Kconfig. Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23powerpc: P1010: Remove macro CONFIG_P1010York Sun
Replace CONFIG_P1010 with ARCH_P1010 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23powerpc: MPC8572: Remove macro CONFIG_MPC8572York Sun
Replace CONFIG_MPC8572 with ARCH_MPC8572 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23powerpc: MPC8569: Remove macro CONFIG_MPC8569York Sun
Replace CONFIG_MPC8569 with ARCH_MPC8569 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23powerpc: MPC8568: Remove macro CONFIG_MPC8568York Sun
Replace CONFIG_MPC8568 with ARCH_MPC8568 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23powerpc: MPC8560: Remove macro CONFIG_MPC8560York Sun
Replace CONFIG_MPC8560 with ARCH_MPC8560 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23powerpc: MPC8555CDS: Remove macro CONFIG_MPC8555CDSYork Sun
Use CONFIG_TARGET_MPC8555CDS instead. Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23powerpc: MPC8555: Remove macro CONFIG_MPC8555York Sun
Replace CONFIG_MPC8555 with ARCH_MPC8555 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23powerpc: MPC8541CDS: Remove macro CONFIG_MPC8541CDSYork Sun
Replace with CONFIG_TARGET_MPC8541CDS from Kconfig. Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23powerpc: mpc8541: Remove macro CONFIG_MPC8541York Sun
Replace CONFIG_MPC8541 with ARCH_MPC8541 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23powerpc: mpc8540: Remove macro CONFIG_MPC8540York Sun
Replace CONFIG_MPC8540 with ARCH_MPC8540 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23powerpc: MPC8536: Move CONFIG_MPC8536 to Kconfig optionYork Sun
Replace CONFIG_MPC8536 with ARCH_MPC8536 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23powerpc: C29XPCIE: Remove macro CONFIG_C29XPCIEYork Sun
Use CONFIG_TARGET_C29XPCIE instead. Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23powerpc: C29X: Move CONFIG_PPC_C29X to Kconfig optionYork Sun
Replace CONFIG_PPC_C29X with ARCH_C29X in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23powerpc: BSC9132QDS: Remove CONFIG_BSC9132QDS macroYork Sun
Use CONFIG_TARGET_BSC9132QDS from Kconfig option, remove CONFIG_BSC9132QDS macro. Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23powerpc: BSC9131/2: Move CONFIG_BSC9131/2 to Kconfig optionsYork Sun
Replace CONFIG_BSC9131, CONFIG_BSC9132 with ARCH_BSC9131, ARCH_BSC9132 Kconfig options. Also drop #ifdef in BSC9131RDB.h since it is redundant. Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23powerpc: MPC8544: Move CONFIG_MPC8544 to Kconfig optionYork Sun
Replace CONFIG_MPC8544 with ARCH_MPC8544 in Kconfig. Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23powerpc: MPC8548: Move CONFIG_MPC8548 to Kconfig optionYork Sun
Replace CONFIG_MPC8548 with ARCH_MPC8548 in Kconfig. Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-22armv8: fsl-layerscape: Support loading 32-bit OS with PSCI enabledAlison Wang
As PSCI and secure monitor firmware framework are enabled, this patch is to support loading 32-bit OS in such case. The default target exception level returned to U-Boot is EL2, so the corresponding work to switch to AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware together. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-22armv8: fsl-layerscape: SMP support for loading 32-bit OSAlison Wang
Spin-table method is used for secondary cores to load 32-bit OS. The architecture information will be got through checking FIT image and saved in the os_arch element of spin-table, then the secondary cores will check os_arch and jump to 32-bit OS or 64-bit OS automatically. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-22armv8: Support loading 32-bit OS in AArch32 execution stateAlison Wang
To support loading a 32-bit OS, the execution state will change from AArch64 to AArch32 when jumping to kernel. The architecture information will be got through checking FIT image, then U-Boot will load 32-bit OS or 64-bit OS automatically. Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-22arm: exynos7420: remove custome low level init functionThomas Abraham
Remove the custom low-level initialization function and reuse the default low-level initialization function. But this requires the ARMV8_MULTIENTRY config option to be enabled for Exynos7420. On Exynos7420, the boot CPU belongs to the second cluster and so with ARMV8_MULTIENTRY config option enabled, the 'branch_if_master' macro fails to detect the CPU as boot CPU. As a temporary workaround the CPU_RELEASE_ADDR is set to point to '_main'. Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Alison Wang <alison.wang@nxp.com> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-22armv8/fsl-lsch3: Update code to release secondary coresPriyanka Jain
NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-22armv8: fsl-layerscape: Add NXP LS2088A SoC supportPriyanka Jain
The QorIQ LS2088A SoC is built on layerscape architecture. It is similar to LS2080A SoC with some differences like 1)Timer controller offset is different 2)It has A72 cores 3)It supports TZASC module Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-22armv8: fsl-layerscape : Check SVR for initializing TZASCPriyanka Jain
LS2080 SoC and its personalities does not support TZASC But other new SoCs like LS2088A, LS1088A supports TZASC Hence, skip initializing TZASC for Ls2080A based on SVR Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-22armv8: fsl-layerscape: Update TZASC registers typePriyanka Jain
TZASC registers like TZASC_GATE_KEEPER, TZASC_REGION_ATTRIBUTES are 32-bit regsiters. So while doing register load-store operations, 32-bit intermediate register, w0 should be used. Update x0 register to w0 register type. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-22armv8: lsch3: Use SVR based timer base address detectionPriyanka Jain
Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-22armv8: lsch3: Add generic get_svr() in assemblyPriyanka Jain
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-22Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini
2016-11-21arm: add save_boot_params for ARM1176Cédric Schieli
Implement a hook to allow boards to save boot-time CPU state for later use. When U-Boot is chain-loaded by another bootloader, CPU registers may contain useful information such as system configuration information. This feature mirrors the equivalent ARMv7 feature. Signed-off-by: Cédric Schieli <cschieli@gmail.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2016-11-21TI: Remove CONFIG_OMAP_COMMON in favor of CONFIG_ARCH_OMAP2Tom Rini
With the move to arch/arm/mach-omap2 there are now very few uses of CONFIG_OMAP_COMMON and further they can all be replaced with CONFIG_ARCH_OMAP2, so do so. Signed-off-by: Tom Rini <trini@konsulko.com>
2016-11-21arm: Introduce arch/arm/mach-omap2 for OMAP2 derivative platformsTom Rini
This moves what was in arch/arm/cpu/armv7/omap-common in to arch/arm/mach-omap2 and moves arch/arm/cpu/armv7/{am33xx,omap3,omap4,omap5} in to arch/arm/mach-omap2 as subdirectories. All refernces to the former locations are updated to the current locations. For the logic to decide what our outputs are, consolidate the tests into a single config.mk rather than including 4. Signed-off-by: Tom Rini <trini@konsulko.com>
2016-11-21arm: Introduce ARCH_OMAP2Tom Rini
To start consolidating various TI-related code, introduce the ARCH_OMAP2 symbol. While we have removed omap2-specific boards some time ago, matching up with the kernel naming here will help overall. Signed-off-by: Tom Rini <trini@konsulko.com>
2016-11-21board: ti: amx3xx: Remove multiple EEPROM readsLokesh Vutla
Detect the board very early and avoid reading eeprom multiple times. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-21ARM: AMx3xx: Centralize early clock initializationLokesh Vutla
This is similar to Commit 93e6253d11030 ("ARM: OMAP4/5: Centralize early clock initialization") that was done for OMAP4+, reflecting the same for AM33xx and AM43xx SoCs to centralize clock initialization. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> [trini: Add setup_early_clocks that calls setup_clocks_for_console for ti81xx] Signed-off-by: Tom Rini <trini@konsulko.com>
2016-11-21armv8/fsl-layerscape: Update CONFIG_LS2080A to CONFIG_FSL_LSCH3Shengzhou Liu
Update CONFIG_LS2080A to CONFIG_FSL_LSCH3 to make those workaround implementing of erratum reusable for more SoCs. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-21armv8: fsl-layerscape: Add README for deploying QSPI imageYuan Yao
Signed-off-by: Yuan Yao <yao.yuan@nxp.com> [YS: Reviese commit subject] Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-21fsl: serdes: fix a deadloop issue for P4080Hou Zhiqiang
This deadloop is introduced by commit: 71fe222 fsl: serdes: ensure accessing the initialized maps of serdes protocol deadloop detail: cpu_init_r => fsl_serdes_init => p4080_erratum_serdes_a005 => is_serdes_configured => fsl_serdes_init Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-21powerpc: mpc512x: Add support for get_svr() for mpc512x devicesSriram Dash
Defines get_svr() for mpc512x devices Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-21armv8: ls2080a: Update serdes protocol supportPriyanka Jain
Add these serdes protocols Serdes1: 0x39, 0x4B, 0x4C, 0x4D Serdes2: 0x47, 0x57 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> [YS: Revise commit message] Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-21armv8: ls1046aqds: add lpuart supportShaohui Xie
LPUART0 is used by default, and it's using platform clock. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-21armv7: Add support of ls1021a-iot boardFeng Li
The patch adds support for Freescale ls1021a-iot board. Signed-off-by: Feng Li <feng.li_2@nxp.com> [YS: rewrite commit message, fix whitespace in Kconfig] Reviewed-by: York Sun <york.sun@nxp.com>
generated by cgit (git 2.34.1) at 2025-01-06 11:58:06 +0000