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2020-07-17x86: acpi: Correct the version of the MADTSimon Glass
Currently U-Boot implements version 2 but reports version 4. Correct it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-17x86: Drop setup_pcat_compatibility()Simon Glass
This function does not exist anymore. Drop it from the header file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17x86: Update the comment about booting for FSP2Simon Glass
The comment here applies only to FSP1, so update it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-17x86: Store the coreboot table address in global_dataSimon Glass
At present this information is used to locate and parse the tables but is not stored. Store it so that we can display it to the user, e.g. with the 'bdinfo' command. Note that now the GD_FLG_SKIP_LL_INIT flag is set in get_coreboot_info(), so it is always set when booting from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-17x86: apl: Adjust FSP-M code to avoid hard-coded addressSimon Glass
Update this code to calculate the address to use, rather than hard-coding it. Obtain the requested stack size from the FSP. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17x86: apl: Set the correct boot mode in the FSP-M codeSimon Glass
If there is MRC information we should run FSP-M with a different boot_mode flag since it is supposed to do a 'fast path' through the memory init. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17x86: Add debugging to table writingSimon Glass
Writing tables is currently pretty opaque. Add a bit of debugging to the process so we can see what tables are written and where they start/end in memory. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-17x86: apl: Fix save/restore of ITSS prioritiesSimon Glass
The FSP-S changes the ITSS priorities. The code that tries to save it before running FSP-S and restore it afterwards does not work as U-Boot relocates in between the save and restore. This means that the driver data saved before relocation is lost and the new driver just sees zeroes. Fix this by allocating space in the relocated memory for the ITSS data. Save it there and access it from the driver after relocation. This fixes interrupt handling on coral. Also drop the log_msg_ret() in irq_first_device_type() since this function can be called speculatively in places where we are not sure if there is an interrupt controller of that type. The resulting log errors are confusing when there is no error. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-17x86: irq: Support flags for acpi_gpeSimon Glass
This binding currently has a flags cell but it is not used. Make use of it to create ACPI tables for interrupts. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-17x86: apl: Hide the p2sb on exit from U-BootSimon Glass
This confuses Linux's PCI probing so needs to be hidden when booting Linux. Add a remove() method to handle this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-17x86: apl: Support set_hide() in p2sb driverSimon Glass
Add support for this new method in the driver and in the fsp-s setup. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-17x86: apl: Use memory-mapped access for VBTSimon Glass
Use the new binman memory-mapping function to access the VBT, to simplify the code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17x86: Add error checking for csrt table generationSimon Glass
Generation of this table can fail, so update the function to return an error code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-17x86: pinctrl: Drop the acpi_path memberSimon Glass
This is in the device tree now, so drop the unnecessary field here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17x86: pinctrl: Update comment for intel_pinctrl_get_pad()Simon Glass
Add information about what is returned on error. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17x86: pinctrl: Add a way to get the pinctrl reg addressSimon Glass
At present we can query the offset of a pinctrl register within the p2sb. For ACPI we need to get the actual address of the register. Add a function to handle this and rename the old one to more accurately reflect its purpose. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-17x86: Add support for building up an NHLT structureSimon Glass
The Intel Non-High-Definition-Audio Link Table (NHLT) table describes the audio codecs and connections in a system. Various devices can contribute information to produce the table. Add functions to allow adding to the structure that is eventually written to the ACPI tables. Also add the device-tree bindings. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-17acpi: Allow creating the GNVS to failSimon Glass
In some cases an internal error may prevent this from working. Update the function return value and report the error. At present the API for writing tables does not easily support reporting errors, but once it is fully updated to use a context pointer, this will be easier. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-17dm: acpi: Enhance acpi_get_name()Simon Glass
For many device types it is possible to figure out the name just by looking at its uclass or parent. Add a function to handle this, since it allows us to cover the vast majority of cases automatically. However it is sometimes impossible to figure out an ACPI name for a device just by looking at its uclass. For example a touch device may have a vendor-specific name. Add a new "acpi,name" property to allow a custom name to be created. With this new feature we can drop the get_name() methods in the sandbox I2C and SPI drivers. They were only added for testing purposes. Update the tests to use the new values. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17x86: Allow devices to write to DSDTSimon Glass
Call the new core function to inject ASL programmatically into the DSDT. This is made up of fragments generated by devices that have the inject_dsdt() method. The normal, compiled ASL file is added after this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17acpi: Add support for DSDT generationSimon Glass
Some devices need to inject extra code into the Differentiated System Descriptor Table (DSDT). Add a method to handle this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct one typo in inject_dsdt() comments] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17x86: Allow devices to write an SSDTSimon Glass
Call the new core function to write the SSDT. This is made up of fragments generated by devices that have the fill_ssdt() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17acpi: Support ordering SSDT data by deviceSimon Glass
Add a /chosen property to control the order in which the data appears in the SSDT. This allows matching up U-Boot's output from a dump of the known-good data obtained from within Linux. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17x86: acpi: Move MADT down a bitSimon Glass
Put this table before MCFG so that it matches the order that coreboot uses when passing tables to Linux. This is a cosmetic change since the order of the tables does not otherwise matter. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17acpi: Add support for SSDT generationSimon Glass
Some devices need to generate code for the Secondary System Descriptor Table (SSDT). Add a method to handle this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17acpi: Support copying properties from device tree to ACPISimon Glass
Some drivers in Linux support both device tree and ACPI. U-Boot itself uses Linux device-tree bindings for its own configuration but does not use ACPI. It is convenient to copy these values over to the ACPI DP table for passing to linux. Add some convenience functions to help with this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17acpi: Add a function to get a device path and scopeSimon Glass
Add a function to build up the ACPI path for a device and another for its scope. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17x86: fsp: Support a warning message when DRAM init is slowSimon Glass
With DDR4, Intel SOCs take quite a long time to init their memory. During this time, if the user is watching, it looks like SPL has hung. Add a message in this case. This works by adding a return code to fspm_update_config() that indicates whether MRC data was found and a new property to the device tree. Also add one more debug message while starting. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-17x86: Avoid #ifdef with CONFIG_HAVE_ACPI_RESUMESimon Glass
At present this enables a few arch-specific members of the global_data struct which are otherwise not part of the struct. As a result we have to use #ifdef in various places. The cost of always having these in the struct is small. Adjust things so that we can use compile-time code instead of #ifdefs. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17x86: p2sb: make P2SB driver depend on P2SB uclassWolfgang Wallner
Currently it is possible to select the P2SB driver without selecting the P2SB uclass, which can't work. Fix this by adding a "depends on" in Kconfig. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-13arm: k3: use correct weak function name spl_board_prepare_for_linuxPatrick Delaunay
Replace the function spl_board_prepare_for_boot_linux by the correct name of the weak function spl_board_prepare_for_linux defined in spl.h. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-07-13arm: k3: Consolidate and silence k3_fit_atf.sh callJan Kiszka
Buiding u-boot-spl-k3[_HS].its is currently unconditionally verbose about what it does. Change that by wrapping the call to k3_fit_atf.sh into a cmd, also using that chance to reduce duplicate lines of makefile code - only IS_HS=1 is different when CONFIG_TI_SECURE_DEVICE is on. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-07-13arm: dts: k3-am65: Sync CPSW DT node from kernelVignesh Raghavendra
Sync CPSW DT node from kernel and move it out of -u-boot.dtsi file. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-07-13arm: dts: k3-j721e: Sync CPSW DT node from kernelVignesh Raghavendra
Sync CPSW DT node from Kernel and move it out of -u-boot.dtsi file. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-07-13arm: dts: k3-am65/j721e: Sync DMA DT bindings from Kernel DTVignesh Raghavendra
Sync DT bindings from kernel DT and move them to out of -u-boot.dtsi files. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
2020-07-11Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-spiTom Rini
- Enable DM_SPI on siemens omap boards (Jagan) - Dropped some non-dm supported omap3 boards (Jagan) - Dropped non-dm code in omap3 spi driver (Jagan) - Dropped non-dm code in kirkwood spi driver (Bhargav)
2020-07-11Merge tag 'uniphier-v2020.10' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier UniPhier SoC updates for v2020.10 - remove workaround for Cortex-A72 - increase U-Boot proper size to 2MB - sync DT with Linux - add system bus controller driver - improve serial driver - add reset assertion to Denali NAND driver
2020-07-11ARM: uniphier: remove NAND reset codeMasahiro Yamada
Now that commit 3e57f879eee6 ("mtd: nand: raw: denali: Assert reset before deassert") added the reset assertion, this code in the board file is unneeded. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11ARM: uniphier: remove sbc/ directoryMasahiro Yamada
Now that this directory contains only uniphier_sbc_boot_is_swapped(), move it to boot-device.c and delete the sbc/ directory entirely. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11bus: uniphier-system-bus: move hardware init from board filesMasahiro Yamada
Move the bus initialization code to this driver from board files. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11bus: uniphier-system-bus: add UniPhier System Bus driverMasahiro Yamada
Since commit 1517126fdac2 ("ARM: uniphier: select DM_ETH"), DM-based drivers/net/smc911x.c is compiled, but it is never probed because the parent node lacks the DM-based driver. I need a skeleton driver to populate child devices (but the next commit will move more hardware settings to the this driver). I put this to drivers/bus/uniphier-system-bus.c because this is the same path as the driver in Linux kernel. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11ARM: uniphier: remove support for NOR Flash on support cardMasahiro Yamada
I actually do not see this used these days because eMMC or NAND is used for non-volatile devices. Dump the burden to maintain this crappy code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11ARM: uniphier: remove unused uniphier_sbc_init_admulti()Masahiro Yamada
This was used by the old sLD3 SoC, the support of which was removed by commit 00aa453ebf56 ("ARM: uniphier: remove sLD3 SoC support"). There is no more user of this function. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11ARM: uniphier: fix build error when CONFIG_MICRO_SUPPORT_CARD=nMasahiro Yamada
If CONFIG_MICRO_SUPPORT_CARD is unset, the build fails due to function redefinition. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11ARM: uniphier: sync with Linux 5.8-rc4Masahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11ARM: uniphier: consolidate SoC select menuMasahiro Yamada
Currently, the supports for the following two ARMv7 SoC groups are exclusive, because the boot ROM loads the SPL to a different address: - LD4, sLD8 (SPL is loaded at 0x00040000) - Pro4, Pro5, PXs2, LD6b (SPL is loaded at 0x00100000) This limitation exists only when CONFIG_SPL=y. Instead of using crappy CONFIG options, checking SPL and SPL_TEXT_BASE is cleaner. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11Revert "ARM: uniphier: add weird workaround code for LD20"Masahiro Yamada
This reverts commit 45f41c134baf5ff1bbf59d33027f6c79884fa4d9. This weird workaround was the best I came up with at that time to boot U-Boot from TF-A. I noticed U-Boot successfully boots on LD20 (i.e. CA72 CPU) by using the latest TF-A. Specifically, since the following TF-A commit, U-Boot runs at EL2 instead of EL1, and this issue went away as a side-effect. |commit f998a052fd94ea082833109f25b94ed5bfa24e8b |Author: Masahiro Yamada <yamada.masahiro@socionext.com> |Date: Thu Jul 25 10:57:38 2019 +0900 | | uniphier: run BL33 at EL2 | | All the SoCs in 64-bit UniPhier SoC family support EL2. | | Just hard-code MODE_EL2 instead of using el_implemented() helper. | | Change-Id: I7ab48002c5205bc8c013e1b46313b57d6c431db0 | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> However, if I reverted that, this problem would come back, presumably because some EL1 code in U-Boot triggers this issue. Now that commit f8ddd8cbb513 ("arm64: issue ISB after updating system registers") fixed this issue properly, this weird workaround is no longer needed irrespective of the exception level at which U-Boot runs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-10Merge tag 'dm-pull-10jul20' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-dm of-platdata: better phandle and compatible-string support patman support for Python3 on Ubuntu 14.04 new checkpatch check to avoid #ifdefs
2020-07-10Merge tag 'rpi-next-2020.10' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-raspberrypi - add support for PCI and XHCI for RPi4 (64 bit only) - optionally reset XHCI device on registration - enable USB_KEYBOARD for rpi_4_defconfig
2020-07-10rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit)Marek Szyprowski
Create a non-cacheable mapping for the 0x600000000 physical memory region, where MMIO registers for the PCIe XHCI controller are instantiated by the PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM 32bit mode, this region is mapped at 0xff800000 CPU virtual address. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
generated by cgit (git 2.34.1) at 2025-02-07 10:28:22 +0000