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2015-02-10imx:mx6 update fuse_bank0_regsPeng Fan
Update fuse_bank0_regs structure according reference mannual. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-02-09Merge branch 'microblaze' of git://git.denx.de/u-boot-microblazeTom Rini
2015-02-09Merge git://git.denx.de/u-boot-arcTom Rini
2015-02-09microblaze: spl: Add LISTS to linker scriptMichal Simek
This is required for driver model. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-02-09microblaze: spl: Do not call mem_malloc_init and use early allocMichal Simek
This patch has some parts connected together: - Use _gd in bss section which is automatically cleared Location at SPL_MALLOC_END wasn't cleared at all - Use MALLOC_F_LEN(early alloc) instead of FULL MALLOC (mem_malloc_init is not called at all) - Simplify malloc and stack init. At the end of SPL addr is malloc area and below is stack Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-02-09microblaze: Add support for CONFIG_SYS_MALLOC_F_LENMichal Simek
Create space for dm_init where calloc is called and malloc_base has to be initialized. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-02-09microblaze: Do not use CONFIG_SYS_GENERIC_GLOBAL_DATAMichal Simek
Because it is not compatible with DM where malloc_base has to be available early and init has to be done in ASM. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-02-09microblaze: Speedup code copyMichal Simek
Remove one instruction in the loop which speedup code copying. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-02-09microblaze: Move architecture to use generic board initMichal Simek
Compile code with -fPIC to get GOT. Do not build SPL with fPIC because it increasing SPL size for nothing. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-02-09microblaze: Fix gd_t address which is placed at the end of BRAMMichal Simek
Setup gd from ASM to be availalbe for board_init_r. Setting it up in spl_board_init is too late when MALLOC is used. Space for gd is located behind MALLOC area at the end of BRAM. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-02-09microblaze: Remove unused asm labelMichal Simek
It is not used at all that's why remove it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-02-09microblaze: Use standard interrupt_init() functionMichal Simek
Do not use microblaze specific interrupt init function. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-02-09microblaze: Remove unneeded data section adding from DTBMichal Simek
DTB is added to rodata section: [ 2] .rodata PROGBITS 84c5b60c 05c60c 00c618 00 A 0 0 4 [ 3] .dtb.init.rodata PROGBITS 84c67c30 068c30 003c80 00 A 0 0 16 [ 4] .rela.dyn RELA 84c6b8b0 06c8b0 000534 0c A 0 0 4 [ 5] .data PROGBITS 84c6bde4 06cde4 001536 00 WA 0 0 16 Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-02-09microblaze: Add debug message about enabling interruptsMichal Simek
Add one more debug message about enabling global interrupts. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-02-09microblaze: Fix coding styleMichal Simek
No functional changes just to pass checkpatch.pl. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-02-09microblaze: Remove DEBUG_INT macro and use debug() insteadMichal Simek
Do not use specific macros for debugging. Also remove compilation warning: w+../arch/microblaze/cpu/interrupts.c: In function 'interrupt_handler': w+../arch/microblaze/cpu/interrupts.c:153:2: warning: format '%x' expects argument of type 'unsigned int', but argument 2 has type 'void (*)(void *)' [-Wformat] w+../arch/microblaze/cpu/interrupts.c:153:2: warning: format '%x' expects argument of type 'unsigned int', but argument 4 has type 'void *' [-Wformat] Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-02-09microblaze: Fix coding style in exception.cMichal Simek
Just coding style cleanup - no functional changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-02-09microblaze: Show return address from exceptionMichal Simek
Show also return address from exception which should suggest where the problem is. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-02-09microblaze: Fix stack usage in interrupt handlerMichal Simek
Do not save registers below r1 stack pointer because it is not checked by stack undeflow is not able to detect it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-02-09common: Move dram_init() declaration to common locationMichal Simek
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-02-09arc: build libgcc in U-BootAlexey Brodkin
This way we may have very limited set of functions implemented so we save some space. Also it allows us to build U-Boot for any ARC core with the same one toolchain because we don't rely on pre-built libgcc. For example: * we may use little-endian toolchain but build U-Boot for ether endianess * we may use non-multilibbed uClibc toolchain but build U-Boot for whatever ARC CPU flavour that current GCC supports Private libgcc built from generic C implementation contributes only 144 bytes to .text section so we don't see significant degradation of size: --->8--- $ arc-linux-size u-boot.libgcc-prebuilt text data bss dec hex filename 222217 24912 214820 461949 70c7d u-boot.libgcc-prebuilt $ arc-linux-size u-boot.libgcc-private text data bss dec hex filename 222361 24912 214820 462093 70d0d u-boot.libgcc-private --->8--- Also I don't notice visible performance degradation compared to pre-built libgcc (where at least "*div*" functions are had-written in assembly) on typical operations of downloading 10Mb uImage over TFTP and bootm. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-02-09arc: move CPU flags selection to the main "config.mk"Alexey Brodkin
As a preparation to ARCv2 port submission we're moving CPU slection flags to a common location. Also it will allow us to have more flexible CPU specification, not only ISA version but CPU family as well checking CONFIG_ARC_CPU_xxx. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-02-09arc: hard-code CONFIG_ARCH_EARLY_INIT_R in asm/config.hAlexey Brodkin
Common arch_early_init_r() is used in "arc/lib/cpu.c" for all ARC boards so there's no sense in separate per-board definitions. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-02-09arc: hard-code CONFIG_SYS_GENERIC_BOARD into asm/config.hAlexey Brodkin
There're no other options for ARC except "generic board" so ther's no point to define CONFIG_SYS_GENERIC_BOARD per board. We now have it set fo all ARC boards. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-02-09arc: add selection of endianess in KconfigAlexey Brodkin
This change allows to keep board description clean and minimalistic. This is especially helpful if one board may house different CPUs with different features. It is applicable to both FPGA-based boards or those that have CPUs mounted on interchnagable daughter-boards. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-02-09arc: select cache settings via menuconfigAlexey Brodkin
This change allows to keep board description clean and minimalistic. This is especially helpful if one board may house different CPUs with different features. It is applicable to both FPGA-based boards or those that have CPUs mounted on interchnagable daughter-boards. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-02-09arc: define and use PTAG AUX regs for MMUv3 onlyAlexey Brodkin
DC_PTAG and IC_PTAG registers only exist in MMUv3. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-02-09arc: add more flavours of ARC700 series CPUAlexey Brodkin
Now we may select a particular version of ARC700: * ARC750D or * ARC770D It allows more flexible (or more fine tuned) configuration of U-Boot. Before that change we relied on minimal configuration but now we may use specific features of each CPU. Moreover allows us to escape manual selection of options that exist in both CPUs but may have say different version like MMUv2 in ARC750D vs MMUv3 in ARC770D. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-02-09arc: memcmp - fix zero-delay loop utilizationIgor Guryanov
It's prohibited to put branch instruction in the very end of zero-delay loop. On execution this causes "Illegal instruction" exception. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
2015-02-07arm, at91: add reset controller status registerHeiko Schocher
add reset controller status register Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Bo Shen <voice.shen@atmel.com>
2015-02-07arm, at91, wdt: do not disable WDT in SPLHeiko Schocher
if CONFIG_AT91SAM9_WATCHDOG is set, do not disable WDT in SPL Signed-off-by: Heiko Schocher <hs@denx.de>
2015-02-07ARM: atmel: cleanup: remove at91cap9 related codeBo Shen
As the at91cap9adk board is removed by commit: b5508344 (ARM: remove broken "at91cap9adk" board), so the at91cap9 code is not used anymore, and also the document for at91cap9 can not be found on www.atmel.com, so remove the at91cap9 related code. Signed-off-by: Bo Shen <voice.shen@atmel.com> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-02-07ARM: atmel: sama5d4_xplained: enable spl supportBo Shen
Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-02-07ARM: atmel: sama5d4ek: enable SPL supportBo Shen
The sama5d4ek support boot up from NAND flash, SD/MMC card and also the SPI flash. Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-02-07ARM: atmel: sama5d4: build related file when enable SPLBo Shen
Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-02-07ARM: atmel: sama5d4: can access DDR in interleave modeBo Shen
The SAMAA5D4 SoC can access DDR in interleave mode. Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-02-07ARM: atmel: sama5d4: add interrupt redirect functionBo Shen
Signed-off-by: Bo Shen <voice.shen@atmel.com> [fix subject] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-02-07ARM: atmel: sama5d4: add bus matrix init functionBo Shen
Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-02-07ARM: atmel: sama5d4: add matrix1 base addr definitionBo Shen
Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-02-07ARM: atmel: spl: can not disable osc for sama5d4Bo Shen
The SAMA5D4 SoC on chip rc oscillator can not be disabled. Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-02-07ARM: atmel: spl: add saic to aic redirect functionBo Shen
Some SoC need to redirect the saic to aic to make the interrupt to work, here add a weak function to be replaced by real function. Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-02-07ARM: atmel: spl: add weak bus matrix init functionBo Shen
Some SoC need to configure the bus matrix, add an weak function to be replace by real function. Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-02-07ARM: atmel: sama5: add sfr register header fileBo Shen
The SFR (special function registers) can be shared bwteen sama5d3 and sama5d4 soc. Signed-off-by: Bo Shen <voice.shen@atmel.com> [whitespace adoptions for 80 char compliance] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-02-07ARM: atmel: sama5: add bus matrix header fileBo Shen
This matrix header file can be shared between sama5d3 and sama5d4 soc. Signed-off-by: Bo Shen <voice.shen@atmel.com> [whitespace adaptions for 80 char compliance] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-02-07ARM: atmel: clock: make it possible to configure HMX32Bo Shen
Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-02-06x86: Use tab instead of space to indent in PCIE_ECAM_BASEBin Meng
Space is used before 'default' in PCIE_ECAM_BASE in arch/x86/Kconfig so it looks misaligned. Replace the space with tab to indent. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06x86: Add SD/MMC support to quark/galileoBin Meng
Intel Galileo board has a microSD slot which is routed from Quark SoC SDIO controller. Enable SD/MMC support so that we can use an SD card. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06x86: Add SPI support to quark/galileoBin Meng
The Quark SoC contains a legacy SPI controller in the legacy bridge which is ICH7 compatible. Like Tunnel Creek and BayTrail, the BIOS control register offset in the ICH SPI driver is wrong for the Quark SoC too, unprotect_spi_flash() is added to enable the flash write. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06x86: galileo: Add GPIO supportBin Meng
Quark SoC has a legacy GPIO block in the legacy bridge (D0:F31), which is just the same one found in other x86 chipset. Since we programmed the GPIO register block base address, we should be able to enable the GPIO support on Intel Galileo board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06x86: quark: Initialize non-standard BARsBin Meng
Quark SoC has some non-standard BARs (excluding PCI standard BARs) which need be initialized with suggested values. This includes GPIO, WDT, RCBA, PCIe ECAM and some ACPI register block base addresses. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
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