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2020-03-31Merge branch 'next' of git://git.denx.de/u-boot-usb into nextTom Rini
2020-03-26rv1108: Fix boot regressionOtavio Salvador
Since commit 79030a486128 ("rockchip: Add Single boot image (with binman, pad_cat)") the following boot regression is seen: U-Boot 2020.04-rc3-00050-gd16e18ca6c-dirty (Mar 09 2020 - 11:40:07 -0300) Model: Elgin RV1108 R1 board DRAM: 128 MiB initcall sequence 67fd12a0 failed at call 6000b927 (err=-22) This happens because the above commit missed to include the "rockchip-u-boot.dtsi" for rv1108, so include this file like it done for other Rockchip SoC dtsi's. Fixes: 79030a486128 ("rockchip: Add Single boot image (with binman, pad_cat)") Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-03-26ARM: dts: Activate pullups in the console pins on rv1108-elgin-r1Otavio Salvador
In order to make the console pins more robust to noise, activate the pullups and increase its drive strength. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-03-24ram: stm32mp1: the property st, phy-cal becomes optionalPatrick Delaunay
This parameter "st,phy-cal" becomes optional and when it is absent the built-in PHY calibration is done. It is the case in the helper dtsi file "stm32mp15-ddr.dtsi" except if DDR_PHY_CAL_SKIP is defined. This patch also impact the ddr interactive mode - the registers of the param 'phy.cal' are initialized to 0 when "st,phy-cal" is not present in device tree (default behavior when DDR_PHY_CAL_SKIP is not activated) - the info 'cal' field can be use to change the calibration behavior - cal=1 => use param phy.cal to initialize the PHY, built-in training is skipped - cal=0 => param phy.cal is absent, built-in training is used (default) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24ram: stm32mp1: increase vdd2_ddr: buck2 for 32bits LPDDRPatrick Delaunay
Need to increase the LPDDR2/LPDDR3 the voltage vdd2_ddr: buck2 form 1.2V to 1.25V for 32bits configuration. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24ARM: dts: stm32mp1: DT alignment with Linux 5.6-rc1Patrick Delaunay
This commit manages diversity for STM32M15x SOCs with: - dedicated files to support all STM32MP15 SOCs family. The differences between those SOCs are: -STM32MP151 [1]: common file. -STM32MP153 [2]: STM32MP151 + CANs + a second CortexA7-CPU. -STM32MP157 [3]: STM32MP153 + DSI + GPU. - new files to manage security diversity on STM32MP15x SOCs. On STM32MP15xY, "Y" gives information: -Y = A means no cryp IP and no secure boot. -Y = C means cryp IP + secure boot. - stm32mp157 pinctrl files to better manage package diversity. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24stm32mp: psci: set cntfrq register of cpu onLudovic Barre
This path allows to set the cntfrq register of targeted cpu. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24stm32mp1: add 800 MHz profile supportPatrick Delaunay
The STM32MP1 series is available in 3 different lines which are pin-to-pin compatible: - STM32MP157: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz, 3D GPU, DSI display interface and CAN FD - STM32MP153: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz and CAN FD - STM32MP151: Single Cortex-A7 core, Cortex-M4 core @ 209 MHz Each line comes with a security option (cryptography & secure boot) & a Cortex-A frequency option : - A : Cortex-A7 @ 650 MHz - C : Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz - D : Cortex-A7 @ 800 MHz - F : Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz This patch adds the support of STM32MP15xD and STM32MP15xF in U-Boot. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24arm: stm32mp: fdt: update kernel device tree according the part numberPatrick Delaunay
Update the kernel device tree for STM32MP15x product lines according the used soc and its part number, when CONFIG_OF_SYSTEM_SETUP is activated: - STM32MP15XA hasn't Crypto (cryp1/2) - STM32M151 and STM32M153 hasn't 3D GPU and DSI host - STM32M151 hasn't CAN FD and has single A7 For example: FDT: cpu 1 node remove for STM32MP151AAA Rev.B FDT: can@4400e000 node disabled for STM32MP151AAA Rev.B FDT: gpu@59000000 node disabled for STM32MP151AAA Rev.B FDT: dsi@5a000000 node disabled for STM32MP151AAA Rev.B Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24arm: stm32mp: add function get_soc_namePatrick Delaunay
Add a function get_soc_name to get a string with the full name of the SOC "STM32MP15xxx Rev.x" Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24arm: stm32mp: improve the error message for smcPatrick Delaunay
Add the SMC code and operation for trace on errors. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24arm: stm32mp: bsec: add permanent lock support in bsec driverPatrick Delaunay
Add BSEC lock access (read / write) at 0xC0000000 offset of misc driver. The write access only available for Trusted boot mode, based on new SMC STM32_SMC_WRLOCK_OTP. With the fuse command, the permanent lock status is accessed with 0x10000000 offset (0xC0000000 - 0x8000000 for OTP sense/program divided by u32 size), for example: Read lock status of fuse 57 (0x39) STM32MP> fuse sense 0 0x10000039 1 Sensing bank 0: Word 0x10000039: 00000000 Set permanent lock of fuse 57 (0x39) STM32MP> fuse prog 0 0x10000039 1 Sensing bank 0: Word 0x10000039: 00000000 WARNING: the OTP lock is updated only after reboot WARING: Programming lock or fuses is an irreversible operation! This may brick your system. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24arm: stm32mp: bsec: remove unneeded testPatrick Delaunay
Remove the test offs < 0 , as offs is unsigned. This patch solves the warnings when compiling with W=1 on stm32mp1 board: In function ‘stm32mp_bsec_read’: arch/arm/mach-stm32mp/bsec.c:368:11: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] 368 | if (offs < 0 || (offs % 4) || (size % 4)) | ^ In function ‘stm32mp_bsec_write’: arch/arm/mach-stm32mp/bsec.c:405:11: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] 405 | if (offs < 0 || (offs % 4) || (size % 4)) | ^ Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-18Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiTom Rini
- Revert "sunxi: psci: avoid error address-of-packed-member"
2020-03-18Revert "sunxi: psci: avoid error address-of-packed-member"Tomasz Duszynski
Using memcpy() for some MMIO access is generally frowned upon and might break things on some platforms. Allwinner H3, which fails to boot, being an example here. Moreover, fields being accessed are naturally aligned and warnings produced by GCC have been quiesced for some time already by: 53dc8ae ("gcc-9: silence 'address-of-packed-member' warning") That said, it should be okay to revert this commit. This reverts commit 9bd34a69a453d409792e08c00953ce8862145e65. Cc: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Tomasz Duszynski <tduszyns@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-03-17Merge tag 'ti-v2020.07-next' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-ti into next K3 J721E: * OSPI boot support * Support for loading remote cores in R5 SPL * PMIC ESM Support * Minor fixes for R5F and C7x remoteproc drivers K3 AM654: * Update AVS class 0 voltages. * Add I2C nodes DRA7xx/AM57xx: * Fixed Android boot on AM57xx AM33/AM43/Davinci: * switch to driver model for the net and mdio driver for baltos * Add DM/DTS support for omap video driver * Enable fastboot on am335x-evm
2020-03-17riscv: Implement new SBI v0.2 extensionsBin Meng
Few v0.1 SBI calls are being replaced by new SBI calls that follows v0.2 calling convention. Implement the replacement extensions and few additional new SBI function calls that makes way for a better SBI interface in future. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-03-17riscv: Introduce a new config for SBI v0.1Bin Meng
We now have SBI v0.2 which is more scalable and extendable to handle future needs for RISC-V supervisor interfaces. Introduce a new config and move all SBI v0.1 code under that config. This allows to implement the new replacement SBI extensions cleanly and remove v0.1 extensions easily in future. Currently, the config is enabled by default. Once all M-mode software, with v0.1, is no longer in use, this config option and all relevant code can be easily removed. This commit is inspired from Linux kernel patch: https://patchwork.kernel.org/patch/11407361/ Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-03-17riscv: Add SBI v0.2 extension definitionsBin Meng
Few v0.1 SBI calls are being replaced by new SBI calls that follows v0.2 calling convention. This patch just defines these new extensions. This commit is inspired from Linux kernel patch: https://patchwork.kernel.org/patch/11407359/ Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-03-17riscv: Add basic support for SBI v0.2Bin Meng
The SBI v0.2 introduces a base extension which is backward compatible with v0.1. Implement all helper functions and minimum required SBI calls from v0.2 for now. All other base extension function will be added later as per need. As v0.2 calling convention is backward compatible with v0.1, remove the v0.1 helper functions and just use v0.2 calling convention. Add a new Kconfig options CONFIG_SBI for the new SBI v0.2 codes, and let CONFIG_SBI_IPI depend on it. This commit is inspired from Linux kernel patch: https://patchwork.kernel.org/patch/11407363/ Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-03-17riscv: Mark existing SBI as v0.1 SBIBin Meng
As per the new SBI specification, current SBI implementation version is defined as 0.1 and will be removed/replaced in future. Each of the function call in 0.1 is defined as a separate extension which makes easier to replace them one at a time. Rename existing implementation to reflect that. This patch is just a preparatory patch for SBI v0.2 and doesn't introduce any functional changes. This commit is inspired from Linux kernel patch: https://patchwork.kernel.org/patch/11407355/ Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-03-17riscv: Avoid calling sbi_clear_ipi()Bin Meng
There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
2020-03-17riscv: Fix sbi_remote_sfence_vma{,_asid}Bin Meng
Currently sbi_remote_sfence_vma{,_asid} does not pass their arguments to SBI at all, which is semantically incorrect. This keeps in sync with Linux kernel commit: a21344dfc6ad: fix sbi_remote_sfence_vma{,_asid} Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
2020-03-16mach-davinci: Hard-code the default SPL_LDSCRIPT pathTom Rini
As there is only one linker script to use in this case, rather than use the BOARDDIR variable hard-code the path. Cc: Lokesh Vutla <lokeshvutla@ti.com> Suggested-by: Masahiro Yamada <masahiroy@kernel.org> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Masahiro Yamada <masahiroy@kernel.org>
2020-03-16edminiv2: Move CONFIG_SPL_LDSCRIPT to defconfigTom Rini
As there is only one machine under mach-orion5x, having a Kconfig entry for SPL_LDSCRIPT is not helpful, move this to the defconfig file. Suggested-by: Masahiro Yamada <masahiroy@kernel.org> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Masahiro Yamada <masahiroy@kernel.org>
2020-03-16Kconfig: Remove redundant variable setsTom Rini
In a few places we have Kconfig entries that set SPL_LDSCRIPT to what is the default value anyways. Drop these. Cc: Michal Simek <monstr@monstr.eu> Cc: Rick Chen <rick@andestech.com> Cc: Philippe Reynes <tremyfr@yahoo.fr> Cc: Eric Jarrige <eric.jarrige@armadeus.org> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com> (for Microblaze) Reviewed-by: Masahiro Yamada <masahiroy@kernel.org>
2020-03-16armv8: K3: j721e: Add DSP internal memory regions in MMU tableSuman Anna
The A72 U-Boot code supports early load and boot of a number of remote processors including the C66_0 and C66_1 DSPs. The current code supports only loading into the DDR regions which were already given the appropriate memory attributes. The C66 DSPs also have L1 and L2 internal memory regions that can behave as normal-memories. Add a new entry to the J721E MMU table covering these regions with the appropriate memory attributes to allow the A72 U-Boot code to support loading directly into these memory regions. Signed-off-by: Suman Anna <s-anna@ti.com>
2020-03-12Merge tag 'u-boot-stm32-20200310' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - stm32mp: fix dependency for CONFIG_STM32_ETZPC
2020-03-11arm: mach-k3: Add a separate function for printing sysfw versionLokesh Vutla
Add a separate function for printing sysfw version so that it can be called independently of k3_sysfw_loader. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-03-10Merge tag 'mmc-2020-3-9' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmcTom Rini
- DM support for CAxxxx SoCs - eMMC board for presidio-asic - Add defer probe for mmc sdhci - TI SoCs mmc misc update
2020-03-10arm: mediatek: remove unused binman configSam Shih
The binman-option BINMAN_FDT is introduced by this commit: commit 3c10dc95bdd0 ("binman: Add a library to access binman entries") BINMAN_FDT being selected when BINMAN=y that resulting in mt7623 and mt7622 are unable to boot. The root cause of this issue is commit: commit cbd2fba1eca1 ("arm: MediaTek: add basic support for MT7629 boards") select BINMAN=y in all mediatek SoCs, and others mediatek SoCs not expect to use BINMAN_FDT. This patch remove BINMAN=y option when ARCH_MEDIATEK=y and move this to the specify SoCs part config. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Tested-by: Frank Wunderlich <frank-w@public-files.de>
2020-03-10stm32mp: update dependency for STM32_ETZPCPatrick Delaunay
Correct the dependency for STM32 ETZPC protection, linked to SOC STM32MP identified by CONFIG_STM32MP15x and not linked to CONFIG_TARGET_STM32MP1 (no more existing). This patch fix an issue introduced by commit 846254888e2e ("stm32mp1: split board and SOC support for STM32MP15x family"). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-10arm: dts: imx8mq-evk: add phy-reset-gpios for fec1Alifer Moraes
Instead of resetting the ethernet phy through functions in imx8mq_evk.c, let the driver reset the phy via dts description adding a reset duration of 10 ms following atheros 8031's datasheet recommendation. Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com>
2020-03-09ARM: dts: imx8mm-verdin: drop rgmii_rxc_dly/txc_dlyMax Krummenacher
The FEC in the i.MX8MM doesn't support this feature. So don't pretend one can use it. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Acked-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2020-03-09ARM: dts: imx8mm-verdin: dm-spl for pinctrl_usdhc1 nodeIgor Opaniuk
Let pinctrl configuration for eMMC node (usdhc1) also be accessible in SPL. Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2020-03-09imx8mm/mn: Add missing root clock entry for ARM core clockFrieder Schrempf
The current implementation in arch/arm/mach-imx/cpu.c uses non-DM code to retrieve the core clock frequency. As the root clock is not listed we currently get: CPU: Freescale i.MX8MMQ rev1.0 at 0 MHz Fix this by adding the missing entry, which results in: CPU: Freescale i.MX8MMQ rev1.0 at 1200 MHz Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-03-09imx: Makefile: added missing ahab.oOliver Graute
added missing ahab.o in Makefile Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-03-09imx: mx6ul_14x14_evk: configure for 24bpp displayAnatolij Gustschin
Before DM_VIDEO conversion this board used 24bpp display configuration, so use it again. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-03-09ARM: dts: imx6sx-sdb: Sync with kernel 5.4.16Fabio Estevam
Sync the imx6sx-sdb dts files with kernel 5.4.16. Signed-off-by: Fabio Estevam <festevam@gmail.com>
2020-03-09ARM: dts: imx6sx: Sync with kernel 5.4.16Fabio Estevam
Sync the imx6sx dts files with kernel 5.4.16. Signed-off-by: Fabio Estevam <festevam@gmail.com>
2020-03-09imx: remove woodburn boardStefano Babic
Board is not longer used, remove it. Signed-off-by: Stefano Babic <sbabic@denx.de>
2020-03-09arm: dts: k3-j721e-r5-common-proc-board: Use unique names for dummy clocksFaiz Abbas
Update the dummy clock names to use unique identifiers. Otherwise the previous node just gets overwitten by the next one with the same name. This fixes eMMC boot not working on J721e-evm. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-03-09arm: K3: sysfw-loader: Add a config_pm_pre_callback()Faiz Abbas
System firmware does not guarantee that clocks going out of the device will be stable during power management configuration. There are some DCRC errors when SPL tries to get the next stage during eMMC boot after sysfw pm configuration. Therefore add a config_pm_pre_callback() to switch off the eMMC clock before power management and restart it after it is done. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-03-09spl: mmc: Fix spl_mmc_get_uboot_raw_sector() implementationFaiz Abbas
The call to spl_mmc_get_uboot_raw_sector() completely ignores and overwrites the raw_sect value passed from the caller of spl_mmc_load(). Fix this by passing raw_sect to the function and returning the same value in the default case. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-03-09mmc: am654_sdhci: Update output tap delay writesFaiz Abbas
With the latest RIOT, there is a different otap delay value for each speed mode. Add a new binding with every supported speed mode. Also disable a given speed mode in the host caps if its corresponding otap-del-sel is not present. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-03-06arm: dts: k3-j721e-r5-common-proc-board: Add ospi1 flash nodeKeerthy
Add ospi1 flash node required for QSPI boot. Signed-off-by: Keerthy <j-keerthy@ti.com>
2020-03-06arm: dts: k3-j721e-mcu-wakeup: Add assigned-clocks/rates properties for ↵Keerthy
ospi1/qspi Add assigned-clocks/rates properties for ospi1/qspi. This is the expected rate as per ROM configuration. Signed-off-by: Keerthy <j-keerthy@ti.com>
2020-03-06arm: dts: k3-j721e: Enable ospi1/qspiKeerthy
Enable the ospi1/qspi for both r5 and a72 configurations. Signed-off-by: Keerthy <j-keerthy@ti.com>
2020-03-05x86: apl: Use cpu_x86_get_count() for cpu_ops.get_countWolfgang Wallner
Use cpu_x86_get_count() to read the number of cores. cpu_x86_get_count() reads the number of CPUs from the device tree. Using this function we can support multiple Apollo Lake variants, e.g.: E3940 (4 cores) and E3930 (2 cores). This was tested on the E3940 and E3930 Apollo Lake variants. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-03-05x86: cpu_x86: Make cpu_x86_get_count() non-staticWolfgang Wallner
The function cpu_x86_get_count() is also useful for other modules. Make it non-static and add a prototype + description. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit (git 2.34.1) at 2024-12-23 23:39:52 +0000