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2019-07-20rockchip: rk322x: default enable SPL LIBCOMMON and LIBGENERICKever Yang
We needs SPL LIBCOMMON and LIBGENERIC for all boards, so we can enable them by default and no need to define in each board. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20rockchip: rk3328: default enable SPL LIBCOMMON and LIBGENERICKever Yang
We needs SPL LIBCOMMON and LIBGENERIC for all boards, so we can enable them by default and no need to define in each board. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20rockchip: rk3399: default enable SPL LIBCOMMON and LIBGENERICKever Yang
We needs SPL LIBCOMMON and LIBGENERIC for all boards, so we can enable them by default and no need to define in each board. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20rockchip: rk3368: use defaule value for SYS_MALLOC_F_LENKever Yang
There is no difference in rk3368 board use for SYS_MALLOC_F_LEN, so we can use default value. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20rockchip: rk3328: use defaule value for SYS_MALLOC_F_LENKever Yang
There is no difference in rk3328 board use for SYS_MALLOC_F_LEN, so we can use default value. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20rockchip: rk3399: use default value for SYS_MALLOC_F_LENKever Yang
There is no difference in rk3399 board use for SYS_MALLOC_F_LEN, so we can use default value. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20rockchip: rk3288: use default value for SYS_MALLOC_F_LENKever Yang
There is no difference in rk3288 board use for SYS_MALLOC_F_LEN, so we can use default value. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20rockchip: rk322x: use defconfig for SYS_MALLOC_F_LENKever Yang
There is no difference in rk322x board use for SYS_MALLOC_F_LEN, so we can use default value. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20rockchip: Kconfig: move ROCKCHIP_BOOT_MODE_REG to soc KconfigKever Yang
Rockchip SoCs have different ROCKCHIP_BOOT_MODE_REG value, move it to SoC's own Kconfig, and add address for rk3128 and rk3328 so that all SoCs have available address. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20rockchip: Kconfig: move rk3399 config into its KconfigKever Yang
Each SoC have its config setting and its Kconfig, move the specific setting to its own Kconfig file. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20rockchip: Kconfig: move rk3368 config into its KconfigKever Yang
Each SoC have its config setting and its Kconfig, move the specific setting to its own Kconfig file. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20rockchip: Kconfig: move rk3288 config into its KconfigKever Yang
Each SoC have its config setting and its Kconfig, move the specific setting to its own Kconfig file. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20rockchip: Kconfig: move rk322x config into its KconfigKever Yang
Each SoC have its config setting and its Kconfig, move the specific setting to its own Kconfig file. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20rockchip: fixup board choice in KconfigKever Yang
Kconfig for board target select is choice option, fixup for rk3036, rk3288 and rv1108. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20rockchip: remove redundant pinctrl header includingKever Yang
No code is using this header file, remove it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20rockchip: rk3288: remove pinctrl init in spl_board_initKever Yang
The pinctrl will default init the io while driver is probe with new pinctrl driver. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20rockchip: rk3188: remove pinctrl init in spl_board_initKever Yang
The pinctrl will default init the io while driver is probe with new pinctrl driver. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20rockchip: rk3399: remove pinctrl init in spl_board_initKever Yang
The pinctrl will default init the io while driver is probe with new pinctrl driver. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20rockchip: dts: rk3399: rock-pi-4: Use LPDDR4-100 dtsiJagan Teki
Use LPDDR4-100 sdram timings dtsi for RockPI-4 board. All these timings are processed during TPL stage of rock-pi-4 board, bootchain. This make TPL would replace rockchip in house rkbin in current bootchain. Bootchain after and before this change: TPL -> SPL -> U-Boot proper rkbin -> SPL -> U-Boot proper Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20rockchip: dts: rk3399: nanopi-neo4: Use DDR3-1866 dtsiJagan Teki
Use DDR3-1866 2GB ddr timings dtsi for 1GB NanoPi Neo4 board. Since sdram rk3399 support dynamic stride and rank detection it can able to detect 1GB ddr eventough the timings are meant for dual channel, 2GB size. Bootchain after and before this change are: TPL -> SPL -> U-Boot proper rkbin -> SPL -> U-Boot proper This certainly fix the second channel data training initialization since we have dynamic rank, stride where second channel capabilities are clear or memset to 0. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21rockchip: dts: rk3399: rockpro64: Use LPDDR4-100 dtsiJagan Teki
Use LPDDR4-100 sdram timings dtsi for Rockpro64 board. All these timings are processed during TPL stage of rockpro64 board, bootchain. This make TPL would replace rockchip in house rkbin in current bootchain. Bootchain after and before this change: TPL -> SPL -> U-Boot proper rkbin -> SPL -> U-Boot proper Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21rockchip: dts: rk3399: Add LPDDR4-100 timingsJagan Teki
Add sdram timings for LPDDR4-100 via rk3399-sdram-lpddr4-100.dtsi file. all timings are dumped from rkbin/bin/rk33/rk3399_ddr_800MHz_v1.20.bin Associated LPDDR4 board -u-boot.dtsi can include this to make these timings available during SPL or TPL stages. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21rockchip: dts: rk3399: Add u-boot, dm-pre-reloc for pmuJagan Teki
Add u-boot,dm-pre-reloc property for pmu in rk3399-u-boot.dtsi so-that SPL can access pmu. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21rockchip: rk3399: syscon: Add pmu supportJagan Teki
Add pmu compatible with relevant U_BOOT_DRIVER for rk3399 via syscon rk3399 driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21arm: include: rockchip: Add rk3399 pmu fileJagan Teki
Add pmu header file for rk3399 SoC, this will help to configure pmu in sdram driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Add DdrModeJagan Teki
Add DdrMode structure with associated bit fields. These would help to reconfigure sdram capabilities during lpddr4 setup related configs. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Add ddrtimingC0Jagan Teki
Add DdrTimingC0 structure with associated bit fields. These would help to reconfigure sdram capabilities during lpddr4 setup related configs. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Add ddr version enc macroJagan Teki
Add dram config macro for handling ddr version number. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Introduce sys_reg3 for more capacity infoJagan Teki
cs0_row, cs1_row and cs1_col needs more bits to show its correct value, update to make use of both sys_reg2, sys_reg3. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com> (Squash similar patches into one patch) Signed-off-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Simply existing dram enc macroJagan Teki
Add simplified and meaningful macro for all setting. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com> (Squash the similar patches into 1 patch) Signed-off-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ARCH: imx: Call sata_remove() not on imx6 duallite/solo boardsLudwig Zenz
For a single binary approach for imx6 quad/dual/duallite/solo it is necessary to enable CONFIG_SATA for quad/dual. On the other hand on imx6 duallite/sole SATA is not available. Therefore sata_remove() is skipped according to a blacklist scheme. Adding further imx derivates is probably not recessary as they are usually not pin-compatible and therefore a different board with its own configuration. Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.com>
2019-07-19imx6dq: Fix chip version issue for rev1.3Ye Li
According to iMX6DQ RM, the minor field (low 8 bits) in DIGPROG is not aligned on silicon revision 1.3. So update get_cpu_rev to correct the revision. 0x00630002 Silicon revision 1.2 0x00630005 Silicon revision 1.3 0x00630006 Silicon revision 1.6 Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19ARM: dts: imx: dh-imx6: Add DHCOM iMX6 Duallite PDK2 device treeLudwig Zenz
This device tree adds support for DHCOM iMX6 duallite and solo deriviates. Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.com> Reviewed-by: Marek Vasut <marex@denx.de>
2019-07-19ARM: dts: dh-imx6: Refactor DT with som and board level defs for use with ↵Ludwig Zenz
imx6 duallite To use the device tree definitions imx6q-dhcom-som.dtsi for all imx6 derivatives rename it to imx6qdl-dhcom.dtsi. We omit the '-som', because it simplifies further mainlinening of already existing device trees. To reuse board level common stuff imx6qdl-dhcom-pdk2.dtsi is created and included by imx6q-dhcom-pdk2.dts. Signed-off-by Ludwig Zenz <lzenz@dh-electronics.com> Reviewed-by: Marek Vasut <marex@denx.de>
2019-07-19arm: dts: imx: fsl-imx8dx.dtsi: add gpio aliases to fix gpio commandAnatolij Gustschin
The gpio command currently uses equal bank names "GPIO0_" for all existing gpio banks, i. e.: U-Boot# gpio status -a Bank GPIO0_: GPIO0_0: input: 0 [ ] GPIO0_1: output: 1 [x] dbg1.gpios ... Bank GPIO0_: GPIO0_0: input: 0 [ ] GPIO0_1: input: 0 [ ] ... So the command is broken, it is not possible to address a desired bank. Add gpio aliases to fix this. Signed-off-by: Anatolij Gustschin <agust@denx.de>
2019-07-19arm: imx8: don't duplicate build_info()Anatolij Gustschin
Move build_info() to common place. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Cc: Peng Fan <peng.fan@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19arm: imx8: factor out uart init codeAnatolij Gustschin
New imx8 boards started adding duplicated UART init code. Factor out this to common function sc_pm_setup_uart(). Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19pico-imx7d: Enable DM_USBJoris Offouga
This patch enable usb support with device-tree Signed-off-by: Joris Offouga <offougajoris@gmail.com> Reviewed-by: Jun Nie <jun.nie@linaro.org>
2019-07-19ARM: imx: m53menlo: Convert WDT support to DMMarek Vasut
Enable DM Watchdog support on iMX53 M53Menlo. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2019-07-19DTS: Add imx6q-display5-u-boot.dtsi file with u-boot specific propertiesLukasz Majewski
This file setups UART5 based serial to be used as pre-relocation console in the U-Boot proper. On purpose pinux configuration is omitted here as it has been already done in SPL. For early pre-relocation code we only need the serial device from DTS. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19DTS: imx: Add display5 board (imx6q based) device tree description (v5.1)Lukasz Majewski
This commit ports from Linux kernel - tag: v5.1 - the device tree description for display5 board. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19imx: imx8dx/qxp: enable thermalPeng Fan
Add thermal dts node Enable thermal in defconfig Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-19misc: imx8: add sc_misc_get_tempPeng Fan
Add sc_misc_get_temp to support get temperature Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-19ARM: dts: imx: Provide 'gpio-ranges' for mxs_gpio driverLukasz Majewski
Those properties are U-Boot specific as the mxs gpio Linux driver (up to version v5.1.11) is not supporting them. Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-07-19ARM: dts: imx: Copy imx28 device tree related files from Linux kernel (v5.1.11)Lukasz Majewski
This patch copies from the Linux kernel stable (tag v5.1.11) SHA1: 17bb763e7eaf i.MX28 related device tree files. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Marek Vasut <marex@denx.de>
2019-07-19spl: imx6: Let spl_boot_device return USDHC1 or USDHC2Adam Ford
Currently, when the spl_boot_device checks the boot device, it will only return MMC1 when it's either sd or eMMC regardless of whether or not it's MMC1 or MMC2. This is a problem when booting from MMC2 if MMC isn't being manually configured like in the DM_SPL case with SPL_OF_CONTROL. This patch will check the register and return either MMC1 or MMC2. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-07-19i.MX6: nand: add nandbcb command for imxShyam Saini
Writing/updating boot image in nand device is not straight forward in i.MX6 platform and it requires boot control block(BCB) to be configured. It becomes difficult to use uboot 'nand' command to write BCB since it requires platform specific attributes need to be taken care of. It is even difficult to use existing msx-nand.c driver by incorporating BCB attributes like mxs_dma_desc does because it requires change in mtd and nand command. So, cmd_nandbcb implemented in arch/arm/mach-imx BCB contains two data structures, Firmware Configuration Block(FCB) and Discovered Bad Block Table(DBBT). FCB has nand timings, DBBT search area, page address of firmware. On summary, nandbcb update will - erase the entire partition - create BCB by creating 2 FCB/DBBT block followed by 1 FW block based on partition size and erasesize. - fill FCB/DBBT structures - write FW/SPL on FW1 - write FCB/DBBT in first 2 blocks for nand boot, up on reset bootrom look for FCB structure in first block's if FCB found the nand timings are loaded for further reads. once FCB read done, DTTB will load and finally firmware will be loaded which is boot image. Refer section "NAND Boot" from doc/imx/common/imx6.txt for more usage information. Reviewed-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Sergey Kubushyn <ksi@koi8.net> Signed-off-by: Shyam Saini <shyam.saini@amarulasolutions.com>
2019-07-19clk: sandbox: Add sandbox test code for Common Clock Framework [CCF]Lukasz Majewski
This patch provides code to implement the CCF clock tree in sandbox. It uses all the introduced primitives; some generic ones are reused, some sandbox specific were developed. In that way (after introducing the real CCF tree in sandbox) the recently added to clk-uclass.c: clk_get_by_id() and clk_get_parent_rate() are tested in their natural work environment. Usage (sandbox_defconfig and sandbox_flattree_defconfig): ./u-boot --fdt arch/sandbox/dts/test.dtb --command "ut dm clk_ccf" Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-07-19dts: sandbox: Add 'osc' clock for Common Clock Framework [CCF] testingLukasz Majewski
This patch adds the 'osc' fixed clock to facilitate the CCF testing in the sandbox U-Boot. It is a starting point for building CCF hierarchy of clocks. Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-07-19ram: rk3399: debug: Add sdram_print_strideJagan Teki
Add code to print the channel stride, this would help to print the stride of associated channel. Here is sample print on LPDDR4, 50MHz. 256B stride Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
generated by cgit (git 2.34.1) at 2025-01-15 08:14:36 +0000