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2018-05-18arm: socfpga: stratix10: Add reset manager driver for Stratix10 SoCLey Foon Tan
Add Reset Manager driver support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-05-18arm: socfpga: stratix10: Add clock manager driver for Stratix10 SoCLey Foon Tan
Add Clock Manager driver support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-05-18arm: socfpga: stratix10: Add watchdog and firewall base addressesLey Foon Tan
Add the base address for watchdog and firewall. Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-05-18ARM: socfpga: Fix Documentation errors in scu_registersBen Kalo
According to ARM Cortex-A9 MPCore TRM section 2.2 - SCU registers Access Control register offset is 0x50. Signed-off-by: Ben Kalo <ben.h.kalo@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
2018-05-18ARM: socfpga: Adding SoCFPGA info for both SPL and U-BootTien Fong Chee
SoC FPGA info is required in both SPL and U-Boot. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2018-05-18ARM: socfpga: Adding clock frequency info for U-BootTien Fong Chee
Clock frequency info is required in U-Boot because info would be erased when transition from SPL to U-Boot. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2018-05-18configs: Add DDR Kconfig support for Arria 10Tien Fong Chee
This patch enables DDR Kconfig support for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18ARM: socfpga: Add DDR driver for Arria 10Tien Fong Chee
Add DDR driver support for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2018-05-18ARM: socfpga: Add DRAM bank size initialization functionTien Fong Chee
Add function for both multiple DRAM bank and single DRAM bank size initialization. This common functionality could be used by every single SOCFPGA board. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Tested-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-05-18ARM: socfpga: Rename the gen5 sdram driver to more specific nameTien Fong Chee
Current sdram driver is only applied to gen5 device, hence it is better to rename sdram driver to more specific name which is related to gen5 device. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2018-05-18ARM: socfpga: Repair A10 EMAC reset handlingMarek Vasut
The EMAC reset and PHY mode configuration was never working on the Arria10 SoC, fix this. This patch pulls out the common code into misc.c and passes the SoC-specific function call in as a function pointer. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18ARM: socfpga: Synchronize Arria10 SoCDK SDMMC handoffMarek Vasut
Regenerate Altera Arria 10 SoCDK SDMMC handoff file using latest Quartus to get the new set of clock bindings in. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18ARM: socfpga: Synchronize Arria10 DTsMarek Vasut
Synchronize Altera Arria 10 DT sources with Linux 4.16.3 as of commit ef8216d28a5920022cddcb694d2d75bd1f0035ca Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18ARM: socfpga: Sort the DT MakefileMarek Vasut
Sort the Makefile entries, no functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18ARM: socfpga: Sync A10 clock manager binding parserMarek Vasut
The A10 clock manager parsed DT bindings generated by Quartus the bsp-editor to configure the A10 clocks. Sadly, those DT bindings changed at some point. The clock manager patch used the old ones, this patch replaces the bindings parser with one for the new set. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18ARM: socfpga: Convert to DM serialMarek Vasut
Pull the serial port configuration from DT and use DM serial instead of having the serial configuration in two places, DT and board config. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18ARM: socfpga: Clean up Kconfig entriesMarek Vasut
Shuffle the default Kconfig entries around so it is not such a mess. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18ARM: socfpga: Zap CONFIG_SOCFPGA_VIRTUAL_TARGETMarek Vasut
This was never used, is not used anywhere and is just in the way by adding annoying ifdeffery. Get rid of it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-17ARM: kirkwood: Add device-tree for sheevaplugChris Packham
Import the dts files from Linux 4.17 and enable device tree control in u-boot. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-17ARM: kirkwood: Add device-tree for pogo_e02Chris Packham
Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-17ARM: kirkwood: Add device-tree for openrdChris Packham
Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-17ARM: kirkwood: Add device-tree for nas220Chris Packham
Import the dts file from Linux 4.17 and enable CONFIG_OF_CONTROL. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-17ARM: kirkwood: Add device-tree for iconnectChris Packham
Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-17ARM: kirkwood: Add device-tree for ib62x0Chris Packham
Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-17ARM: kirkwood: Add device-tree for guruplugChris Packham
Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-17ARM: kirkwood: Add device-tree for goflexhomeChris Packham
Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-17ARM: kirkwood: Add device-tree for dockstarChris Packham
Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-17ARM: kirkwood: Add device-tree for dns325Chris Packham
Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-17ARM: add devicetree files for kirkwood SoCChris Packham
These files are taken verbatim from the Linux kernel 4.17 Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-15nds32: Define PLATFORM__CLEAR_BIT for generic_clear_bit()Bryan O'Donoghue
nds2 bitops.h provides a __clear_bit() but does not define PLATFORM__CLEAR_BIT as a result generic_clear_bit() is used instead of the architecturally provided __clear_bit(). This patch defines PLATFORM__CLEAR_BIT which means that __clear_bit() in nds32 bitops.h will be called whenever generic_clear_bit() is called - as opposed to the default cross-platform generic_clear_bit(). Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie> Cc: Macpaul Lin <macpaul@andestech.com>
2018-05-15nds32: Define PLATFORM__SET_BIT for generic_set_bit()Bryan O'Donoghue
nds32 bitops.h provides a __set_bit() but does not define PLATFORM__SET_BIT as a result generic_set_bit() is used instead of the architecturally provided __set_bit(). This patch defines PLATFORM__SET_BIT which means that __set_bit() in nds32 bitops.h will be called whenever generic_set_bit() is called - as opposed to the default cross-platform generic_set_bit(). Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie> Cc: Macpaul Lin <macpaul@andestech.com>
2018-05-15nios2: Define PLATFORM__CLEAR_BIT for generic_clear_bit()Bryan O'Donoghue
nios2 bitops.h provides a __clear_bit() but does not define PLATFORM__CLEAR_BIT as a result generic_clear_bit() is used instead of the architecturally provided __clear_bit(). This patch defines PLATFORM__CLEAR_BIT which means that __clear_bit() in nios2 bitops.h will be called whenever generic_clear_bit() is called - as opposed to the default cross-platform generic_clear_bit(). Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie> Cc: Thomas Chou <thomas@wytron.com.tw>
2018-05-15nios2: Define PLATFORM__SET_BIT for generic_set_bit()Bryan O'Donoghue
nios2 bitops.h provides a __set_bit() but does not define PLATFORM__SET_BIT as a result generic_set_bit() is used instead of the architecturally provided __set_bit(). This patch defines PLATFORM__SET_BIT which means that __set_bit() in nios2 bitops.h will be called whenever generic_set_bit() is called - as opposed to the default cross-platform generic_set_bit(). Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie> Cc: Thomas Chou <thomas@wytron.com.tw>
2018-05-15riscv: Define PLATFORM__CLEAR_BIT for generic_clear_bit()Bryan O'Donoghue
riscv bitops.h provides a __clear_bit() but does not define PLATFORM__CLEAR_BIT as a result generic_clear_bit() is used instead of the architecturally provided __clear_bit(). This patch defines PLATFORM__CLEAR_BIT which means that __clear_bit() in riscv bitops.h will be called whenever generic_clear_bit() is called - as opposed to the default cross-platform generic_clear_bit(). Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie> Cc: Rick Chen <rick@andestech.com> Cc: Greentime Hu <green.hu@gmail.com>
2018-05-15riscv: Define PLATFORM__SET_BIT for generic_set_bit()Bryan O'Donoghue
riscv bitops.h provides a __set_bit() but does not define PLATFORM__SET_BIT as a result generic_set_bit() is used instead of the architecturally provided __set_bit(). This patch defines PLATFORM__SET_BIT which means that __set_bit() in x86 bitops.h will be called whenever generic_set_bit() is called - as opposed to the default cross-platform generic_set_bit(). Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie> Cc: Rick Chen <rick@andestech.com> Cc: Greentime Hu <green.hu@gmail.com>
2018-05-15x86: Define PLATFORM__SET_BIT for generic_set_bit()Bryan O'Donoghue
x86 bitops.h provides a __set_bit() but does not define PLATFORM__SET_BIT as a result generic_set_bit() is used instead of the architecturally provided __set_bit(). This patch defines PLATFORM__SET_BIT which means that __set_bit() in x86 bitops.h will be called whenever generic_set_bit() is called - as opposed to the default cross-platform generic_set_bit(). Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
2018-05-15Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini
2018-05-15dts: sunxi: add PWM node for sun50iVasily Khoruzhick
Add PWM definition to sun50i-a64.dtsi Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2018-05-15pwm: sunxi: add support for PWM found on Allwinner A64Vasily Khoruzhick
This commit adds basic support for PWM found on Allwinner A64. It can be used for pwm_backlight driver (e.g. for Pinebook) Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2018-05-14net: add Kconfig for MVGBEChris Packham
Add Kconfig for MVGBE and update boards to select this. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2018-05-14ARM: mvebu: a38x: move sys_env_device_rev_getChris Packham
Move sys_env_device_rev_get() from the ddr training code to sys_env_lib.c (which currently resides with the serdes code). This brings sys_env_device_rev_get() into line with sys_env_device_id_get() and sys_env_model_get(). Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14ARM: mvebu: a38x: move definition of PEX_CFG_DIRECT_ACCESSChris Packham
PEX_CFG_DIRECT_ACCESS was defined in ddr3_hws_hw_training_def.h despite only being used in the serdes code. Move this definition to ctrl_pex.h where all the other PEX defines are. Also remove the duplicate definition of PEX_DEVICE_AND_VENDOR_ID which is already defined in ctrl_pex.h. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14arm64: mvebu: Add basic support for the Turris Mox boardMarek Behún
This adds basic support for the Turris Mox board from CZ.NIC, which is currently being crowdfunded on Indiegogo. Turris Mox is as modular router based on the Armada 3720 SOC (same as EspressoBin). The basic module can be extended by different modules. The device tree binary for the kernel can be dependent on which modules are connected, and in what order. Because of this, the board specific code creates in U-Boot a variable called module_topology, which carries this information. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14watchdog: Add support for Armada 37xx CPU watchdogMarek Behún
This adds support for the CPU watchdog found on Marvell Armada 37xx SoCs. There are 4 counters which can be set as CPU watchdog counters. This driver uses the second counter (ID 1, counting from 0) (Marvell's Linux also uses second counter by default). In the future it could be adapted to use other counters, with definition in the device tree. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14spi: mvebu_a3700_spi: Use Armada 37xx clk driver for SPI clock frequencyMarek Behún
Since now we have driver for clocks on Armada 37xx, use it to determine SQF clock frequency for the SPI driver. Also change the default config files for Armada 37xx devices so that the clock driver is enabled by default, otherwise the SPI driver cannot be enabled. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14driver: clk: Add support for clocks on Armada 37xxMarek Behún
The drivers are based on Linux driver by Gregory Clement. The TBG clocks support only the .get_rate method. - since setting rate is not supported, the driver computes the rates when probing and so subsequent calls to the .get_rate method do not read the corresponding registers again The peripheral clocks support methods .get_rate, .enable and .disable. - the .set_parent method theoretically could be supported on some clocks (the parent would have to be one of the TBG clocks) - the .set_rate method would have to try all the divider values to find the best approximation of a given rate, and it doesn't seem like this should be needed in U-Boot, therefore not implemented Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14phy: marvell: a3700: Use comphy_mux on Armada 37xx.Marek Behún
Lane 0 supports SGMII1 and USB3. Lane 1 supports SGMII0 and PEX0. Lane 2 supports SATA0 and USB3. This is needed for Armada 37xx. This introduces new device tree bindings. AFAIK there is currently no driver for Armada 37xx comphy in Linux. When such a driver will be pushed into Linux, this will need to be rewritten accordingly. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-11Merge git://git.denx.de/u-boot-tegraTom Rini
2018-05-11Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblazeTom Rini
Xilinx changes for v2018.07 microblaze: - Align defconfig zynq: - Rework fpga initialization and cpuinfo handling zynqmp: - Add ZynqMP R5 support - Wire and enable watchdog on zcu100-revC - Setup MMU map for DDR at run time - Show board info based on DT and cleanup IDENT_STRING zynqmp tools: - Add read partition support - Add initial support for Xilinx bif format for boot.bin generation mmc: - Fix get_timer usage on 64bit cpus - Add support for SD3.0 UHS mode nand-zynq: - Add support for 16bit buswidth - Use address cycles from onfi params scsi: - convert ceva sata to UCLASS_AHCI timer: - Add Cadence TTC for ZynqMP r5 watchdog: - Minor cadence driver cleanup
2018-05-11Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
generated by cgit (git 2.34.1) at 2025-01-05 22:14:50 +0000