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2019-09-05clk: aspeed: Add support for SD clockEddie James
Add code to enable the SD clock on the ast2500 SoC. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Eddie James <eajames@linux.ibm.com>
2019-09-03Merge tag 'arc-for-2019.10-rc4' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-arc These are some very late changes mostly required to get 64-bit division working on ARC boards. For that we had to import missing parts of libgcc and add compiler flags to EMSDP which otherwise used very simple profile for compliation. And while at it another fix for EM SDP initialization is inluded as well.
2019-09-03arc: libgcc: Import __udivdi3 & __udivmoddi4 to allow 64-bit divisionAlexey Brodkin
As reported by Kever here [1] we were unable to compile 64-bit division code due to missing definition of __udivdi3(). Import its implementation and __udivmoddi4() as its direct dependency from today's libgcc [2]. [1] https://patchwork.ozlabs.org/patch/1146845/ [2] https://github.com/gcc-mirror/gcc/commit/5d8723600bc0eed41226b5a6785bc02a053b45d5 Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Kever Yang <kever.yang@rock-chips.com>
2019-09-03Merge tag 'for-v2019.10-v2' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-i2c i2c bugfixes for 2019.10 take 2 - i2c: mxc: add CONFIG_CLK support If CONFIG_CLK is enabled use clk framework for clock settings.
2019-09-03riscv: cache: use CCTL to flush d-cacheRick Chen
Use CCTL command to do d-cache write back and invalidate instead of fence. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-03riscv: dts: move out AE350 L2 node from cpus nodeRick Chen
When L2 node exists inside cpus node, uclass_get_device can not parse L2 node successfully. So move it outside from cpus node. Also add tag-ram-ctl and data-ram-ctl attributes for v5l2 cache controller driver. This can adjust timing by requirement from dtb to improve performance. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-03riscv: cache: Flush L2 cache before jump to linuxRick Chen
Flush and disable L2 cache in dcache_disable() which will be called in cleanup_before_linux() before jump to linux. The sequence will be preferred as below: L1 flush -> L1 disable -> L2 flush -> L2 disable Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-03riscv: ax25: add imply v5l2 cache controllerRick Chen
Select the v5l2 UCLASS_CACHE driver for ax25. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-03riscv: andes_plic: init plic by scanning each cpu nodeRick Chen
Initialize plic driver by ofnode_for_each_subnode() instead of cpu_get_count(). This way can support to skip some harts which maybe marked as unavailable, but the cpu node exists indeed. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-03riscv: update fix_rela_dynMarcus Comstedt
The addend is now added for RELOC_TYPE relocs. Also, changed the loop structure so that all the R_RISCV_RELATIVE relocs are not required to be at the beginning of the list. Signed-off-by: Marcus Comstedt <marcus@mc.pp.se> Cc: Rick Chen <rick@andestech.com>
2019-09-02i2c: mxc: add CONFIG_CLK supportPeng Fan
When CONFIG_CLK enabled, use CLK UCLASS for clk related settings. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> hs: removed hunk in mxc_i2c_probe() as not longer in code
2019-09-01Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
- r8a66597 usb changes
2019-08-31Revert "vexpress64: fvp dram: add DRAM configuration"Ryan Harkin
This reverts commit fc04b923541d984b1544056fd3bfa8129d4e5aac where the FVP DRAM configuration was added. Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Sudeep Holla <sudeep.holla@arm.com>
2019-08-30board_f: fix noncached reservation calculationStephen Warren
The current code in reserve_noncached() has two issues: 1) The first update of gd->start_addr_sp always rounds down to a section start. However, the equivalent calculation in cache.c:noncached_init() always first rounds up to a section start, then subtracts a section size. These two calculations differ if the initial value is already rounded to section alignment. 2) The second update of gd->start_addr_sp subtracts exactly CONFIG_SYS_NONCACHED_MEMORY, whereas the equivalent calculation in cache.c:noncached_init() rounds the noncached size up to section alignment before subtracting it. The two calculations differ if the noncached region size is not a multiple of the MMU section size. In practice, one/both of those issues causes a practical problem on Jetson TX1; U-Boot triggers a synchronous abort during initialization, likely due to overlapping use of some memory region. This change fixes both these issues by duplicating the exact calculations from noncached_init() into reserve_noncached(). However, this fix assumes that gd->start_addr_sp on entry to reserve_noncached() exactly matches mem_malloc_start on entry to noncached_init(). I haven't traced the code to see whether it absolutely guarantees this in all (or indeed any!) cases. Consequently, I added some comments in the hope that this condition will continue to be true. Fixes: 5f7adb5b1c02 ("board_f: reserve noncached space below malloc area") Cc: Vikas Manocha <vikas.manocha@st.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2019-08-29Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xxTom Rini
Enable DM PCI for T2080RDB, T4240RDB, T1024RDB, T1042D4RDB, P1020RDB, P2020RDB, P2041RDB, P3041DS, P4080DS, and MPC8548CDS
2019-08-28MPC8548: dts: Added PCIe DT nodeHou Zhiqiang
MPC8548 integrated a PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 1.0a, and this patch is to add DT node for the PCIe controller. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28P5040: dts: Added PCIe DT nodesHou Zhiqiang
P5040 integrated 3 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 2.0, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28P4080: dts: Added PCIe DT nodesHou Zhiqiang
P4080 integrated 3 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 2.0, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28P3041: dts: Added PCIe DT nodesHou Zhiqiang
P3041 integrated 4 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 2.0, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28P2041: dts: Added PCIe DT nodesHou Zhiqiang
P2041 integrated 3 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 2.0, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28P2020: dts: Added PCIe DT nodesHou Zhiqiang
P2020 integrated 3 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 1.0a, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28P1020: dts: Added PCIe DT nodesHou Zhiqiang
P1020 integrated 2 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 1.0a, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28t104x: dts: Added PCIe DT nodesHou Zhiqiang
T104x integrated 4 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 2.0, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28t102x: dts: Added PCIe DT nodesHou Zhiqiang
T102x integrated 3 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 2.0, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28t4240: dts: Added PCIe DT nodesHou Zhiqiang
T4240 integrated 4 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 3.0, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-27Merge branch 'u-boot-stm32_20190827' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - Fixes and update related to STM32MP1 platforms
2019-08-27Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xxTom Rini
Support of device tree model for T2080RDB, T4240RDB, T1024RDB, T1042D4RDB, P1020RDB, P2020RDB, P2041RDB, P3041DS, P4080DS, P5040DS and MPC8548CDS. Also support of i2c dm model.
2019-08-27stm32mp1: Add remoteproc support for m4 coprocessorPatrick Delaunay
Alignment with kernel patch proposal for binding: [PATCH v4 0/8] stm32 m4 remoteproc on STM32MP157c https://lkml.org/lkml/2019/5/14/159 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27bsec: update after MISC u-class updatePatrick Delaunay
Since the commit 8729b1ae2cbd ("misc: Update read() and write() methods to return bytes xfered"); The misc bsec driver need to be adapted to reflect the number of transferred bytes. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27stm32mp1: Makefile cleanupPatrick Delaunay
Don't compile psci for SPL build. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27stm32mp1: board: Update the way vdd-supply is retrieved from DTPatrick Delaunay
Due to kernel DT alignment, pwr-supply is renamed to vdd-supply and is a subnode of pwr-regulators. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27stm32mp1: board: support of error led on ed1/ev1 boardPatrick Delaunay
Create a function led_error_blink and add node in device tree. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27stm32mp1: board: enable v1v2_hdmi and v3v3_hdmi regulator on dk2 bootPatrick Delaunay
As for Audio codec IC, HDMI IC is not "IO safe". HDMI regulators (v3v3 and v1v2) must be enabled to allow I2C1 bus usage. HDMI IC must be under reset during power up and keep HDMI and AUDIO devices in reset while they are not used in U-Boot to keep them in low power mode (each device can be kept in reset independently keeping their power supplies ON until kernel). Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27stm32mp1: configs: add spi load support in splPatrick Delaunay
Add the boot for NOR, SPL load U-Boot.img at offset CONFIG_SYS_SPI_U_BOOT_OFFS = 0x80000. It is the start address of mtd partition ssbl in nor. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27stm32mp1: configs: add condition to activate WATCHDOG in SPLPatrick Delaunay
Only activate WATCHDOG in SPL when CONFIG_WATCHDOG is activated in U-Boot. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27stm32mp1: configs: imply CONFIG_OF_LIBFDT_OVERLAYPatrick Delaunay
Add imply for FDT overlay that can be usefuill for kernel device tree management but it is not mandatory (can be removed to gain space) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27stm32mp1: configs: Activate DISABLE_CONSOLEPatrick Delaunay
Activate DISABLE_CONSOLE needed for stm32prog support on uart. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27stm32mp1: configs: select CONFIG_STM32_SERIALPatrick Delaunay
Select the serial driver mandatory for the console. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27stm32mp1: configs: activate PRE_CONSOLE_BUFFERPatrick Delaunay
Correctly handle silent=1 in the default environment. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27stm32mp1: configs: activate CONFIG_SILENT_CONSOLEPatrick Delaunay
Allow to disable console with environment variable 'silent': > env set silent 1; env save Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27stpmic1: program pmic to keep only the debug unit onPatrick Delaunay
Depending on backup register value, we maintain the debug unit powered-on for debugging purpose. Only BUCK1 is required for powering the debug unit, so revert the setting for all the other power lanes, except BUCK3 that has to be always on. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27ARM: dts: stm32mp1: add pull-up on serial rx of console connected to STLINKPatrick Delaunay
Avoid U-Boot auto-boot interruption for line break detection on console when the RX line connected to STLINK is floating (-IO error in getc cause by framing error and testc return 1) Same workaround is applied on all the STMicroelectonics board. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27ARM: dts: stm32mp1: add key support on DK1/DK2Patrick Delaunay
Allow to use PA13 and PA14 to force fastboot mode or STM32CubeProgrammer mode. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27ARM: dts: stm32mp1: add ldtc pre-reloc proper in SOC filePatrick Delaunay
The pre-relocation probe is needed to reserve video frame buffer in video_reserve() for all the board; LDTC must be tagged prereloc in SOC U-Boot dtsi file. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27ARM: dts: stm32mp1: Add PSCI node access before relocationPatrick Delaunay
Add node in DT and avoid error to search UCLASS_SYSRESET in board_f.c::print_resetinfo() and lost 1.6s in U-Boot for the trusted boot chain. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27ARM: dts: stm32mp1: Add iwdg2 support for SPLPatrick Delaunay
This patch adds independent watchdog support for stm32mp157c in SPL. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27ARM: dts: stm32mp1: DDR config v1.45Patrick Delaunay
Update DDR configuration with the latest update: - Change DQSGE to 1 for DDR3, to cure missing DQS preamble. Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27ARM: dts: stm32mp1: sync device tree with v5.3-rc2Patrick Delaunay
Synchronize device tree with v5.3-rc2 label and update the associated u-boot dtsi. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27ARM: dts: stih410-b2260: Sync DT with kernel v5.2Patrice Chotard
Synchronize U-boot DT with kernel v5.2 for stih410-b2260. Update stih410-b2260-u-boot.dtsi accordingly. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-08-26Merge branch '2019-08-26-master-imports'Tom Rini
- Assorted minor bugfixes
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