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2016-11-22armv8: fsl-layerscape: Support loading 32-bit OS with PSCI enabledAlison Wang
As PSCI and secure monitor firmware framework are enabled, this patch is to support loading 32-bit OS in such case. The default target exception level returned to U-Boot is EL2, so the corresponding work to switch to AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware together. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-22armv8: fsl-layerscape: SMP support for loading 32-bit OSAlison Wang
Spin-table method is used for secondary cores to load 32-bit OS. The architecture information will be got through checking FIT image and saved in the os_arch element of spin-table, then the secondary cores will check os_arch and jump to 32-bit OS or 64-bit OS automatically. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-22armv8: Support loading 32-bit OS in AArch32 execution stateAlison Wang
To support loading a 32-bit OS, the execution state will change from AArch64 to AArch32 when jumping to kernel. The architecture information will be got through checking FIT image, then U-Boot will load 32-bit OS or 64-bit OS automatically. Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-22arm: exynos7420: remove custome low level init functionThomas Abraham
Remove the custom low-level initialization function and reuse the default low-level initialization function. But this requires the ARMV8_MULTIENTRY config option to be enabled for Exynos7420. On Exynos7420, the boot CPU belongs to the second cluster and so with ARMV8_MULTIENTRY config option enabled, the 'branch_if_master' macro fails to detect the CPU as boot CPU. As a temporary workaround the CPU_RELEASE_ADDR is set to point to '_main'. Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Alison Wang <alison.wang@nxp.com> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-22armv8/fsl-lsch3: Update code to release secondary coresPriyanka Jain
NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-22armv8: fsl-layerscape: Add NXP LS2088A SoC supportPriyanka Jain
The QorIQ LS2088A SoC is built on layerscape architecture. It is similar to LS2080A SoC with some differences like 1)Timer controller offset is different 2)It has A72 cores 3)It supports TZASC module Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-22armv8: fsl-layerscape : Check SVR for initializing TZASCPriyanka Jain
LS2080 SoC and its personalities does not support TZASC But other new SoCs like LS2088A, LS1088A supports TZASC Hence, skip initializing TZASC for Ls2080A based on SVR Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-22armv8: fsl-layerscape: Update TZASC registers typePriyanka Jain
TZASC registers like TZASC_GATE_KEEPER, TZASC_REGION_ATTRIBUTES are 32-bit regsiters. So while doing register load-store operations, 32-bit intermediate register, w0 should be used. Update x0 register to w0 register type. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-22armv8: lsch3: Use SVR based timer base address detectionPriyanka Jain
Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-22armv8: lsch3: Add generic get_svr() in assemblyPriyanka Jain
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-21armv8/fsl-layerscape: Update CONFIG_LS2080A to CONFIG_FSL_LSCH3Shengzhou Liu
Update CONFIG_LS2080A to CONFIG_FSL_LSCH3 to make those workaround implementing of erratum reusable for more SoCs. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-21armv8: fsl-layerscape: Add README for deploying QSPI imageYuan Yao
Signed-off-by: Yuan Yao <yao.yuan@nxp.com> [YS: Reviese commit subject] Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-21fsl: serdes: fix a deadloop issue for P4080Hou Zhiqiang
This deadloop is introduced by commit: 71fe222 fsl: serdes: ensure accessing the initialized maps of serdes protocol deadloop detail: cpu_init_r => fsl_serdes_init => p4080_erratum_serdes_a005 => is_serdes_configured => fsl_serdes_init Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-21powerpc: mpc512x: Add support for get_svr() for mpc512x devicesSriram Dash
Defines get_svr() for mpc512x devices Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-21armv8: ls2080a: Update serdes protocol supportPriyanka Jain
Add these serdes protocols Serdes1: 0x39, 0x4B, 0x4C, 0x4D Serdes2: 0x47, 0x57 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> [YS: Revise commit message] Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-21armv8: ls1046aqds: add lpuart supportShaohui Xie
LPUART0 is used by default, and it's using platform clock. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-21armv7: Add support of ls1021a-iot boardFeng Li
The patch adds support for Freescale ls1021a-iot board. Signed-off-by: Feng Li <feng.li_2@nxp.com> [YS: rewrite commit message, fix whitespace in Kconfig] Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-17Merge tag 'signed-efi-next' of git://github.com/agraf/u-bootTom Rini
Patch queue for efi - 2016-11-17 Highlights this time around: - x86 efi_loader support - hello world efi test case - network device name is now representative - terminal output reports modes correctly - fix psci reset for ls1043/ls1046 - fix efi_add_runtime_mmio definition for x86 - efi_loader support for ls2080
2016-11-17armv8: fsl-layerscape: Add support for efi_loader RTS resetAlexander Graf
When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-17armv8: ls2080a: Declare spin tables as reserved for efi loaderAlexander Graf
The efi loader code has its own memory map, so it needs to be aware where the spin tables are located, to ensure that no code writes into those regions. Signed-off-by: Alexander Graf <agraf@suse.de>
2016-11-17ls2080: Exit dpaa only right before exiting U-BootAlexander Graf
On ls2080 we have a separate network fabric component which we need to shut down before we enter Linux (or any other OS). Along with that also comes configuration of the fabric using a description file. Today we always stop and configure the fabric in the boot script and (again) exit it on device tree generation. This works ok for the normal booti case, but with bootefi the payload we're running may still want to access the network. So let's add a new fsl_mc command that defers configuration and stopping the hardware to when we actually exit U-Boot, so that we can still use the fabric from an EFI payload. For existing boot scripts, nothing should change with this patch. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> [agraf: Fix x86 build]
2016-11-17efi_loader: Disable PSCI reset for ls1043 and ls1046Alexander Graf
The NXP ls1043 and ls1046 systems do not (yet) have PSCI enablement for reset. Don't enable generic PSCI reset code on them. Signed-off-by: Alexander Graf <agraf@suse.de>
2016-11-15ARM64: zynqmp: Adding prefetchable memory space to pcieBharat Kumar Gogada
Adding prefetchable memory space to pcie device tree node. Shifting configuration space to 64-bit address space. Removing pcie device tree node from amba as it requires size-cells=<2> in order to access 64-bit address space. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: Add clocks for LPDDMAKedareswara rao Appana
Zynqmp DMA driver expects two clocks (main clock and apb clock) For LPDDMA channels the two clocks are missing in the Dma node resulting probe failure. xilinx-zynqmp-dma ffa80000.dma: main clock not found. xilinx-zynqmp-dma ffa80000.dma: Probing channel failed xilinx-zynqmp-dma: probe of ffa80000.dma failed with error -2 This patch fixes this issue. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: Add description for LPDDMA channel usageKedareswara rao Appana
LPDDMA default allows only secured access. inorder to enable these dma channels, one should ensure that it allows non secure access. This patch updates the same. Reported-by: Sai Pavan Boddu <saipava@xilinx.com> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: Use 64bit size cell format for main amba busMichal Simek
Use 64bit size cell for main amba bus instead of 32bit because PCIe node requires it Change 64bit sizes also for all others IPs. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: Add ocm node in dtsiNaga Sureshkumar Relli
This patch adds ocm controller node in zynqmp.dtsi. needed for OCM edac support. Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: Add device tree properties for ZynqMP GT coreAnurag Kumar Vulisha
This patch adds the ZynqMP GT core device-tree properties for zynqmp.dtsi file. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Tested-by: Hyun Kwon <hyunk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15Revert "ARM64: zynqmp: Added broken-tuning property to SD, eMMC nodes"Michal Simek
This reverts commit bd750e7a6c515c081b72d4ef108a2bfa691a3fd1 Implemented the new workaround for auto tuning based on zynqmp compatible string, so removed the 'broken-tuning' property. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: change sdhci compatible string.Sai Krishna Potthuri
This patch changes the compatible string for sdhci node, adds "xlnx,device_id" and "xlnx,mio_bank" property to sdhci node. Signed-off-by: Sai Krishna Potthuri <lakshmis@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: List all SMMU idsMichal Simek
Add SMMU description for all tested IPs. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: Add support for zynqmp fpga managerNava kishore Manne
Add support for zynqmp fpga manager. Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: Add cortexa53 edac nodeNaga Sureshkumar Relli
This patch adds edac node for arm cortexa53 to report errors on L1 and L2 caches. Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15Revert "ARM64: zynqmp: Add serdes address space dp driver"Michal Simek
This reverts commit 786db82bd5bf09cc8f78c8b14445e843d7566b1c. Since we are using serdes driver , no need of mapping serdes register space into DP driver. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Tested-by: Hyun Kwon <hyunk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: drm: Add DMA indexHyun Kwon
Each plane can be associated with multiple DMA channels. So add index for each DMA channel. Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: Sync gpio node propertiesMichal Simek
Keep dtsi in sync with mainline kernel. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: Remove xlnx,id propertyMichal Simek
Remove unused xlnx,id property because it is not the part of DT binding. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: pci: Updating device tree as per upstreamBharat Kumar Gogada
Updating required device tree changes as per mainlined driver from 4.6 kernel. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: Support for multiple PM IDs assigned to a PM domainFilip Drazic
Previously, it was assumed that there is a 1:1 mapping between PM ID defined in the platform firmware and a PM domain. However, there can be a situation where multiple PM IDs belong to a single PM domain (e.g. PM IDs for GPU and two pixel processors correspond to a single PM domain). This patch adds support for assigning more than one PM ID to a single PM domain. Updated documentation accordingly. Assigned pixel processors PM IDs to GPU PM domain. Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: DT: Add PM domains for GPU and PCIEFilip Drazic
Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: DT: Remove unused PM domains for PLLFilip Drazic
Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: DT: Remove unused DDR PM domainFilip Drazic
DDR power states are handled by the PM firmware, so this domain is redundant. Also, since there is no device using this PM domain, it will be powered off during boot, which is wrong. Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: Remove note about level shifter on zcu102Michal Simek
i2c device is just level shifter. Remove reference from dts. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: Add dcc port to dtsiMichal Simek
Add dcc to dtsi for supporting system without serial port. DCC is enabled by default on ZynqMP. Adding dcc to zcu100 and zcu102 which were tested. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: Add gpio-keys for zcu102Michal Simek
There is gpio push button on MIO22. Add it to DTS to have full board description. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: Enable gpio-led as heartbeat on zcu102Michal Simek
Show user that Linux is alive on the board. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: Enable can1 for ep108Naga Sureshkumar Relli
This patch enables can1 for ep108. Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Reviewed-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: Added clocks to DT for ep108VNSL Durga
Added clks for ep108 platform. Signed-off-by: VNSL Durga <vnsldurg@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: Add clocks for LPDDMAKedareswara rao Appana
Zynqmp DMA driver expects two clocks (main clock and apb clock) LPDDMA clock cofiguration is missing for the same in the zynqmp-clk.dtsi file. This patch updates for the same. Reported-by: Sai Pavan Boddu <saipava@xilinx.com> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: Remove DTC 1.4.2 warningsMichal Simek
DTC 1.4.2 reports these warnings: Warning (unit_address_vs_reg): Node /amba_apu has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /amba has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /amba/usb@fe200000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/usb@fe300000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-video0channel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-video1channel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-video2channel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-graphicschannel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-audio0channel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-audio1channel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name This patch is fixing them. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
generated by cgit (git 2.34.1) at 2025-01-27 16:00:06 +0000