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2020-09-24armv8: dts: fsl-lx2160a: add gpio0 gpio1 gpio3 DT nodeshui.song
add gpio0 gpio1 gpio3 DT nodes to fsl-lx21600.dtsi Signed-off-by: hui.song <hui.song_1@nxp.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24armv8: lx2160a: fix reset sequenceMeenakshi Aggarwal
Make sure that SW_RST_REQ and RST_REQ_MSK are cleared before triggering hardware reset request. Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24arm64: Layerscape: Survive LPI one-way reset workaroundHou Zhiqiang
The workaround of LPI one-way reset issue is broken by the series: https://patchwork.ozlabs.org/project/uboot/list/?series=192398 This patch is to add DT node for GIC RD tables and create corresponding reserved-memory node in kernel DT to fix it. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24fsl-layerscape: enable dwc3 snooping featureRan Wang
Configure DWC3’s cache type to ‘cacheable’ for better performance. Actually related register definition and values are SoC specific, which means this setting is only applicable to Layerscape SoC, not generic for all platforms which have integrated DWC3 IP. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-23mips: vocore2: fix various issuesMauro Condarelli
- fix SPL image generation - fix incorrect console output - increase malloc_f and malloc_r space to fix LZMA decompression errors - increase SPI flash clock Signed-off-by: Mauro Condarelli <mc5686@mclink.it> [squashed to one patch, fix commit subject and description] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2020-09-23mips: dts: Fix PIC32MZDA GPIO register definitionsJohn Robertson
The GPIO bank name for banks J and K are not correct when using the 'gpio' command from the console. The driver derives the bank name from the device tree instance string by using the instance value and adding 'A': gpio0@xxaddrxx is Bank A, gpio1@yyaddryy is Bank B and so on. On the PIC32, there is no Bank I so instances 8 and 9 need to be incremented as a minimum change. An alternative (less opaque) implementation would be to use a bank-name property instead but this would require modifying the driver code too. Signed-off-by: John Robertson <john.robertson@simiatec.com>
2020-09-23mips: dts: Fix PIC32MZDA GPIO register definitionsJohn Robertson
GPIO state cannot be changed via the device tree (e.g. with gpio-hog) or using the 'gpio' command from the console. The root cause is a discrepancy between the driver and the device tree: the driver code expects an absolute I/O address in the <reg> property, while the device tree defines the address relative to a declaration in the parent pinctrl node. Changing the device tree to fix a driver issue would normally be wrong, however: - I have run the first version of U-Boot in which this driver appears (v2016.03) and the same problem exists, so this is not a regression; - There is no code that references a parent device tree node that might suggest the intent of the author was to parse the DT as it exists now; - The equivalent Linux PIC32 GPIO driver also uses absolute addresses for the GPIO <reg> property. This change brings the U-Boot DT more into line with Linux. Additionally, the data sheet (Microchip ref. 60001361H) shows that the register set to control a GPIO bank spans 0xE0 bytes, but the device tree specified size is only 0x48 bytes. Signed-off-by: John Robertson <john.robertson@simiatec.com>
2020-09-23mips: dts: Fix device tree warnings for PIC32MZDAJohn Robertson
Signed-off-by: John Robertson <john.robertson@simiatec.com>
2020-09-23mips: pic32mzdask: disable SDHCI SDCD signal workaroundJohn Robertson
The PIC32MZ DA Starter Kit does not need the card detect workaround because the SDCD signal line is connected properly. Disable the workaround in this case. Signed-off-by: John Robertson <john.robertson@simiatec.com>
2020-09-21x86: acpi: Add memset to initialize SPCR tableWolfgang Wallner
Add a missing memset to acpi_create_spcr(). The other acpi_create_xxxx() functions perform a memset on their structures, acpi_create_spcr() does not and as a result the contents of this table are partly uninitialized (and thus random after every reset). Fixes: b288cd960072 ("x86: acpi: Generate SPCR table") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fix the tags format in the commit message] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-21x86: acpi: Fix calculation of DSDT lengthWolfgang Wallner
Currently, the calculation for the length of the DSDT table includes any bytes that are added for alignment, but those bytes are not initialized. This is because the DSDT length is calculated after a call to acpi_inc_align(). Split this up into the following sequence: * acpi_inc() * Calculate DSDT length * acpi_align() Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-21x86: fsp: Replace e-mmc with emmc in devicetree bindingsWolfgang Wallner
The term eMMC is used inconsistently within the FSP devicetree bindings (e-mmc and emmc), especially for "emmc-host-max-speed" documentation and code disagree. Change all eMMC instances within the FSP bindings to consistently use "emmc". The term "emmc" is already used a lot within U-Boot, while "e-mmc" is only used in the FSP bindings. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct one typo in the commit message] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-17apalis-imx8qm: rename all occurences to apalis-imx8Philippe Schenker
The Toradex product is called apalis-imx8 consisting of SoM with i.MX8QM and i.MX8QP SoCs. Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2020-09-17colibri-imx8qxp: rename all occurences to colibri-imx8xPhilippe Schenker
The Toradex product is called colibri-imx8x consisting of SoM with i.MX8QXP and i.MX8DX SoCs. Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2020-09-17ARM: mx6: ddr: Add support for iMX6UL/ULL/SL/SDLMarek Vasut
This patch adds support for iMX6UL/ULL/SL/SDL MMDC into the DDR calibration code. The difference between MX6DQ and MX6UL/ULL/SL is that the later SoCs have 2 SDQS registers, just like MX6SX, while the MX6DQ/MX6SDL has 8. Fixes: 4f4c128c65 ("ARM: mx6: ddr: Add support for iMX6SX") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eric Nelson <eric@nelint.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-09-17imx8mp: Remove parts MIMX8ML7 and MIMX8ML5 supportPeng Fan
Latest datasheet revE has removed MIMX8ML7D/5D/7C/5C parts, so update u-boot to remove decoding and support for those parts. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-09-17imx8m: clock_imx8mm: add missed returnPeng Fan
Add missed return Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-09-17imx8mq: fix SSCG_PLL_REFCLK_SEL_xPeng Fan
Fix SSCG_PLL_REFCLK_SEL_x, the offset starts from 0, not 16 Reported-by: Coverity 3448860 Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2020-09-17imx8mq: fix FRAC_PLL_REFCLK_SEL_MASKPeng Fan
Coverity reported dead code, however it is FRAC_PLL_REFCLK_SEL_MASK was wrongly set. Reported-by: Coverity 10045172 Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2020-09-17imx7: ccm: correct target interface numPeng Fan
According to i.MX 7Dual Applications Processor Reference Manual, Rev. 1 The target interface CCM root index ranges [0,124], so the number should be 125. Reported-by: Coverity 18045 Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2020-09-16Merge tag 'efi-2020-10-rc5' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for efi-2020-10-rc5 The following bugs are fixed: * unaligned access in br_i32_decode() * missing restore of global data pointer in UEFI selftest * missing restore of global data pointer on RISC-V in UEfI subsystem * efi_var_mem_notify_exit_boot_services() should not be __efi_runtime
2020-09-16rockchip: make_fit_atf: ignore empty PT_LOAD segmentHeinrich Schuchardt
The linker sometimes creates PT_LOAD segments with length (p_filesz) zero as described in https://man7.org/linux/man-pages/man5/elf.5.html. This leads to build failures. We should ignore empty segments. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Tested-by: Tom Rini <trini@konsulko.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-09-16rockchip: rv1108: Enable grf as pre-reloc nodeKever Yang
The grf node will be used before relocate, enable it in dts. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-09-14riscv: define function set_gd()Heinrich Schuchardt
Function set_gd() is needed in the UEFI sub-system if the global data pointer is stored in a register. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-12ARM: MediaTek: amend IC description for MediaTek MT8512Mingming Lee
The description for MT8512 has some mistake, so correct it. Signed-off-by: Mingming Lee <Mingming.Lee@mediatek.com>
2020-09-09ARM: dts: stm32: Adjust PLL4 settings on AV96 againMarek Vasut
PLL4Q is supplying both FDCAN and LTDC. In case HDMI is in use, the 50 MHz generated from PLL4Q cannot be divided well enough to produce accurate clock for HDMI pixel clock. Adjust it to generate 74.25 MHz instead. The PLL4P/PLL4R are generating 99 MHz instead of 100 MHz, which is in tolerance for the SDMMC. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Gerald Baeza <gerald.baeza@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-09ARM: dts: stm32: Pull UART4 RX high on AV96Marek Vasut
There is no dedicated pull resistor on the AV96 UART4 (console UART) pin. In case there is no UART adapter installed on the AV96, the line is floating and can trigger reception of garbage characters, which in turn can abort U-Boot autoboot. Add default pull up to mitigate this problem. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-09arm: stm32mp: cleanup test on eth_env_set_enetaddr resultPatrick Delaunay
Remove the unnecessary inversion on the eth_env_set_enetaddr() result which only make complex the code of setup_mac_address() and display an invalid value in the associated pr_err. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Marek Vasut <marex@denx.de>
2020-09-03Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini
- Mostly DFU fixes and r8152 fixes
2020-09-03arm: socfpga: soc64: Check FPGA Config status register before bridge resetChee Hong Ang
Instead of querying SDM for FPGA configuration status through mailbox messages, U-Boot now checks System Manager's FPGA Config status register for FPGA configuration status before resetting bridge. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-09-01spl: add g_dnl_get_board_bcd_device_numberPeng Fan
Add g_dnl_get_board_bcd_device_number, the new BCD value is used by uuu to distinguish if the SPL supports the SDPV. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-09-01fastboot: Extend fastboot_set_reboot_flag with reboot reasonRoman Kovalivskyi
Extend fastboot_set_reboot_flag arguments with reboot reason so that it could handle different reboot cases in future. Signed-off-by: Roman Kovalivskyi <roman.kovalivskyi@globallogic.com>
2020-09-01x86: Drop nhlt_serialise()Simon Glass
This function is not actually used in U-Boot. Drop it. Suggested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-01x86: Introduce USE_EARLY_BOARD_INIT optionAndy Shevchenko
Introduce USE_EARLY_BOARD_INIT option and select it by the actual users. Cc: George McCollister <george.mccollister@gmail.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-08-31Merge tag 'ti-v2020.10-rc4' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-ti - Update to ABI 3.0 - Fix i2c write in eeprom driver
2020-08-31arm: dts: a37x0: enable sd card support on espressobinWilson Ding
Enabled SDIO slot 0 (south bridge) for SD card on Espressobin board. Change-Id: I51a2debf9fba276b9c4a2bc6da91328d47f443e3 Signed-off-by: Wilson Ding <dingwei@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/60945 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> [pali: Define cd-gpios and enable CONFIG_DM_REGULATOR_GPIO] Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Andre Heider <a.heider@gmail.com>
2020-08-31arm64: a37xx: pci: Make PCIe Reset GPIO DT compatible with Linux kernel DTPali Rohár
Change active-high to active-low and change DT property name from reset-gpio to reset-gpios. This format of gpio reset is used by pci-aardvark driver in Linux kernel. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Konstantin Porotchkin <kostap@marvell.com> Tested-by: Andre Heider <a.heider@gmail.com>
2020-08-31arm64: dts: armada-3720-espressobin: fix COMPHY nodesMarek Behún
This commit fixes initialization of COMPHY on EspressoBin. Commit 22f418935be4 ("phy: marvell: a3700: Use comphy_mux on Armada 37xx.") introduced usage of comphy_mux on Armada 37xx comphy driver. The lanes are defined in comphy_a3700.c as described in functional specification, that is: lane 0 is SGMII1 or USB3 lane 1 is PCIe or SGMII0 lane 2 is SATA or USB3 But the DTS for EspressoBin configures PCIe on lane 0 and USB3 on lane 1, which is wrong in the sense of the specification and doesn't work with the comphy_mux code, which is 2 years now (the aardvark driver causes synchronous abort in U-Boot). It worked till the above mentioned commit, because the code for powering up PCIe PHY doesn't work with lane number at all, and the code for powering up USB3 PHY works differently only if USB3 is on lane 2, ie. the check goes like: if (lane == 2) something else something else so it does not differentiate between lanes 0 and 1. In the future I shall post patches that remove the comphy_a3700 driver and add comphy driver which uses calls to ATF, like Linux' driver does. This will have the advantage of same DTS bindings as Linux', but till this is done, we need this patch. Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Pali Rohár <pali@kernel.org> Cc: Stefan Roese <sr@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Andre Heider <a.heider@gmail.com>
2020-08-31arm: dts: k3-am65: Update the RM resource typesLokesh Vutla
Update the ringacc and udma dt nodes to use the latest RM resource types similar to the ones used in k3-j721e dt nodes. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-08-27arc: Kconfig: Add missing DM dependencyMichal Simek
ARC is selecting TIMER which depends on DM but DM is not selected and doesn't need to be enabled. Fix it by selecting DM for ARC architecture. Kconfig is showing this missing dependency by: WARNING: unmet direct dependencies detected for TIMER Depends on [n]: DM [=n] Selected by [y]: - ARC [=y] && <choice> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-25Merge tag 'u-boot-imx-20200825' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx For 2020.10 ----------- - mx6: SOCs user selectable Fix for imx6q_logic Some DM conversion - mx7: introduce secondary boot device Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/720918010 Signed-off-by: Tom Rini <trini@konsulko.com>
2020-08-25Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini
- Add basic Marvell/Cavium OcteonTX/TX2 support (Suneel) - Infrastructure changes to PCI uclass to support these SoC's (Suneel) - Add PCI, MMC & watchdog driver drivers for OcteonTX/TX2 (Suneel) - Increase CONFIG_SYS_MALLOC_F_LEN for qemu-x86 (Stefan)
2020-08-25Merge tag 'u-boot-rockchip-20200820' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - Fix rk3399 evb sdcard support - Fix for SPL_LED support
2020-08-25Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscvTom Rini
- Sipeed Maix support S-mode. - Provide command sbi. - Use fdtdec_get_addr_size_auto_parent to get fu540 cache base address. - Fix a compiler error with CONFIG_SPL_SMP=n. - Fix sifive ram driver 32 compiler warnings. - Fix kendryte/pll.h redefine nop() warning.
2020-08-25arm: mx6: Make all i.MX6 SoCs user-selectableTom Rini
We have a number of platforms that are a combination of a carrier board and System-on-Module (SoM) that in turn allows for the board to have different SoCs on it. In some cases, this is handled via board-specific Kconfig options. In other cases we make use of CONFIG_SYS_EXTRA_OPTIONS. This latter case however can lead to invalid configurations as we will not in turn get options that in Kconfig are selected by or depend on that setting. To resolve this, make the SoC option a choice in Kconfig and make boards depend on what they can support. This change opens us up for further clean-ups in the cases where a single CONFIG_TARGET_xxx can support different SoCs and today they do not, or do not cleanly do so. Reported-by: Matt Porter <mporter@konsulko.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com> Cc: Soeren Moch <smoch@web.de> Cc: Markus Niebel <Markus.Niebel@tq-group.com> Cc: Igor Opaniuk <igor.opaniuk@toradex.com> Cc: Heiko Schocher <hs@denx.de> Cc: Hannes Schmelzer <hannes.schmelzer@br-automation.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Andreas Geisreiter <ageisreiter@dh-electronics.de> Cc: Ludwig Zenz <lzenz@dh-electronics.de> Cc: Lukasz Majewski <lukma@denx.de> Cc: Akshay Bhat <akshaybhat@timesys.com> Cc: Ken Lin <Ken.Lin@advantech.com.tw> Cc: Ian Ray <ian.ray@ge.com> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Raffaele RECALCATI <raffaele.recalcati@bticino.it> Cc: Simone CIANNI <simone.cianni@bticino.it> Cc: Adam Ford <aford173@gmail.com> Cc: Marcin Niestroj <m.niestroj@grinn-global.com> Cc: "Eric Bénard" <eric@eukrea.com> Cc: Baruch Siach <baruch@tkos.co.il> Cc: Jason Liu <jason.hui.liu@nxp.com> Cc: Ye Li <ye.li@nxp.com> Cc: Eric Nelson <eric@nelint.com> Cc: Troy Kisky <troy.kisky@boundarydevices.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Parthiban Nallathambi <parthiban@linumiz.com> Cc: Marek Vasut <marex@denx.de> Cc: "Sébastien Szymanski" <sebastien.szymanski@armadeus.com> Cc: Christian Gmeiner <christian.gmeiner@gmail.com> Cc: Niel Fourie <lusus@denx.de> Cc: Martyn Welch <martyn.welch@collabora.com> Cc: Richard Hu <richard.hu@technexion.com> Cc: Stefan Roese <sr@denx.de> Cc: Boris Brezillon <bbrezillon@kernel.org> Cc: Arkadiusz Karas <arkadiusz.karas@somlabs.com> Cc: Breno Lima <breno.lima@nxp.com> Cc: Francesco Montefoschi <francesco.montefoschi@udoo.org> Cc: Silvio Fricke <open-source@softing.de> Tested-by: Matt Porter <mporter@konsulko.com> [colibri_imx6] Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Marcin Niestroj <m.niestroj@grinn-global.com>
2020-08-25arm: octeontx2: Add support for OcteonTX2 SoC platformsSuneel Garapati
This patch adds support for all OcteonTX2 96xx/95xx boards from Marvell. For 96xx boards, use octeontx_96xx_defconfig and for 95xx boards, use octeontx_95xx_defconfig. Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
2020-08-25arm: octeontx: Add support for OcteonTX SoC platformsSuneel Garapati
This patch adds support for all OcteonTX 81xx/83xx boards from Marvell. For 81xx boards, use octeontx_81xx_defconfig and for 83xx boards, use octeontx_83xx_defconfig. Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
2020-08-25arm: octeontx2: Add headers for OcteonTX2Suneel Garapati
Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
2020-08-25arm: octeontx: Add headers for OcteonTXSuneel Garapati
Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-25arm: include/asm/io.h: Add 64bit clrbits and setbits helpersSuneel Garapati
Add 64bit API for clrbits and setbits. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org>