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2017-09-18rockchip: dts: rk3399-puma: replace 'rockchip, vbus-gpio' with fixed regulatorPhilipp Tomsich
On the RK3399-Q7, we need to turn on the on-module USB hub before using the USB host interfaces (only the OTG interface is directly connected to the edge connector). This drops the deprecated 'rockchip,vbus-gpio' property and uses a fixed regulator to turn on the USB hub. References: 26a8b80 "usb: host: xhci-rockchip: use fixed regulator to control vbus" Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-18rk3288: Add Vyasa initial board supportJagan Teki
This patch adds support for Vyasa RK3288 initial board from Amarula Solutions. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18rockchip: rk3399: spl: remove hard-coded addresses for GRF and SGRFPhilipp Tomsich
On the RK3399, we will have either OF_PLATDATA or full OF_CONTROL enabled: this allows the use of syscon to retrieve the addresses of GRF and SGRF (except for the early debug UART setup, which runs so early that the device-model is not initialised). This removes the hard-coded addresses and goes through syscon to retrieve the base-addresses of GRF and SGRF. After that, we use the structure definitions to locate the respective registers. In addition to this, the inclusion of header files is also cleaned up: - all headers are included at the beginning (there was a spurious inclusion of the grf header from within a function) - all #include statements for unused headers are removed - the remaining #include statements are sorted (while keeping common.h included in front) Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-18rockchip: dts: rk3368-lion: add /chosen/tick-timerPhilipp Tomsich
To support bootstage recording, we want to mark our DM timer as the tick-timer; this triggers the support for 'trying harder' to read the timer in the Rockchip DM timer driver, even if the device model isn't ready yet. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18rockchip: rk322x: Disable integrated macphy for saving power consumingDavid Wu
Unfortunately, the integrated macphy default is enabled, which will increase power consuming, if we do not use this PHY. So let's disable it at first, which will save power consuming. If we really use it, then enable it in driver level. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18rockchip: rk322x: enable fastboot to set boot mode tagKever Yang
To support fastboot "fastboot reboot-bootloader" cmd. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18ARM: dts: rockchip: add USB nodes for evb-rv1108William Wu
This patch adds USB OTG/EHCI/OHCI nodes for evb-rv1108 USB ports. Signed-off-by: William Wu <william.wu@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18imx: imx7d: remove CamelCase from ENET_xMHz macrosEric Nelson
Update these macros to use all upper-case to avoid checkpatch warnings: ENET_25MHz, ENET_50MHz, ENET_125MHz, Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-09-18imx_common: detect USB serial downloader reliablyStefan Agner
The current mechanism using SCR/GPR registers work well when the serial downloader boot mode has been selected explicitly (either via boot mode pins or using bmode command). However, in case the system entered boot ROM due to unbootable primary boot devices (e.g. empty eMMC), the SPL fails to detect that it has been downloaded through serial loader and tries to continue booting from eMMC: Trying to boot from MMC1 mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ### The only known way to reliably detect USB serial downloader is by checking the USB PHY receiver block power state... Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com>
2017-09-18Merge git://git.denx.de/u-boot-uniphierTom Rini
2017-09-18imx: add macro to detect whether USB PHY is activeStefan Agner
This macro allows to detect whether the USB PHY is active. This is helpful to detect if the boot ROM has previously started the USB serial downloader. The idea is taken from the mfgtool support in the NXP U-Boot: http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/commit/?h=imx_v2016.03_4.1.15_2.0.0_ga&id=a352ed3c5184b95c4c9f7468f5fbb5f43de5e412 Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com>
2017-09-18ARM: uniphier: add GPU(Mali) reset deassert and clk enableMasahiro Yamada
The driver for Linux is out of control of Socionext, so set up reset / clock in here. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-09-18ARM: uniphier: remove bit field macros from sc64-regs.hMasahiro Yamada
Starting from PXs3, the bit fields of RSTCTRL, CLKCTRL registers will change every SoC. There is no more point to define bitfields in the common header file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-09-18ARM: uniphier: merge two defconfig files into uniphier_v7_defconfigMasahiro Yamada
The main difference between Pro4 and PXs2/LD6b is the Denali NAND IP version. This is now distinguished by DT. Merge the two defconfig files into uniphier_v7_defconfig. Update the README.uniphier too. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-09-16x86: ivybridge: remove unused variablesHeinrich Schuchardt
legacy_hole_base_k and legacy_hole_size_k are defined but not used. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-16dm: x86: Allow TSC timer to be used before DM is readySimon Glass
With bootstage we need access to the timer before driver model is set up. To handle this, put the required state in global_data and provide a new function to set up the device, separate from the driver's probe() method. This will be used by the 'early' timer also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-16x86: Support Intel Cherry Hill boardBin Meng
This adds support to Intel Cherry Hill board, a board based on Intel Braswell SoC. The following devices are validated: - serial port as the serial console - on-board Realtek 8169 ethernet controller - SATA AHCI controller - EMMC/SDHC controller - USB 3.0 xHCI controller - PCIe x1 slot with a graphics card - ICH SPI controller with an 8MB Macronix SPI flash - Integrated graphics device as the video console Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16x86: braswell: Disable PUNIT power configuration for B0 steppingBin Meng
FSP's built-in UPD configuration enables PUNIT power configuration, but on B0 stepping, this causes CPU hangs in fsp_init(). Disable it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16x86: braswell: Add FSP configurationBin Meng
Add FSP related configuration for Braswell. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16x86: braswell: Add microcode for B0/C0/D0 stepping SoCBin Meng
This adds microcode device tree fragment for Braswell B0 (406C2), C0 (406C3) and D0 (406C4) stepping SoC. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16x86: Add Intel Braswell SoC supportBin Meng
This adds initial Intel Braswell SoC support. It uses Intel FSP to initialize the chipset. Similar to its predecessor BayTrail, there are some work to do to enable the legacy UART integrated in the Braswell SoC. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16x86: fsp: Update fsp command to show spec 1.1 headerBin Meng
FSP spec 1.1 adds 3 new APIs and their offsets are in the header. Update the 'fsp hdr' command to show these new entries. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16x86: dm: video: Add a framebuffer driver that utilizes VBTBin Meng
When a VBT is given to an FSP that supports graphics initialization, the FSP will produce a graphics info HOB that contains all necessary information for the linear frame buffer of the integrated graphics device. This adds a DM video driver for it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16x86: dts: Include Intel Video BIOS Table in the ROM imageBin Meng
Now that binman is able to recognize the Video BIOS Table entry, add such one in the u-boot.dtsi. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16x86: Add Video BIOS Table (VBT) related Kconfig optionsBin Meng
This adds Kconfig options for Video BIOS Table which is normally required if you are using an Intel FSP firmware that is complaint with spec 1.1 or later to initialize the integrated graphics device. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16x86: fsp: Add FSP_GRAPHICS_INFO_HOBBin Meng
This adds a new HOB type for graphics information introduced in FSP spec 1.1. When graphics capability is included in FSP and enabled, FSP produces an FSP_GRAPHICS_INFO_HOB as described in the EFI PI specification which provides information about the graphics mode and framebuffer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16x86: fsp: Update struct common_buf for FSP spec 1.1Bin Meng
FSP spec 1.1 adds one more member to the struct common_buf to determine the memory size that can be reserved by FSP below "top of low usable memory" for bootloader usage. This new member uses the reserved space so that it is still compatible with previous FSP spec 1.0. A new HOB (FSP_HOB_RESOURCE_OWNER_BOOTLOADER_TOLUM_GUID) is also published when common_buf.tolum_size is valid and non zero. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-15ARM: davinci: Remove CONFIG_SOC_DA830Adam Ford
Nothing CONFIG_SOC_DA830 anymore, so let's remove it and the one remaining source file for it. It appears to have been abandoned a while ago. Signed-off-by: Adam Ford <aford173@gmail.com>
2017-09-15arm: dts: Add missing u-boot specific dtsi for dra7-evmJean-Jacques Hiblot
commit b63b995 (arm: dts: Add u-boot specific compatibles) separated out u-boot specific compatibles from dts files. The u-boot specifics were moved in *-u-boot.dtsi files for all dra7 platforms except dra7-evm. Without it the SD card is broken on DRA7-evm because the regulator cannot be enabled. Fix it by adding the missing dra7-evm-u-boot.dtsi with the needed properties. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-09-15arm: mach-omap2: Relax checks on OP-TEE location to allow pageable imageHarinarayan Bhatta
When the OP-TEE image is built for secure paging the load address may be in SRAM, remove checks that prevent this. Signed-off-by: Harinarayan Bhatta <harinarayan@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-09-15blk: Remove various places that do flush cache after readBin Meng
All these places seem to inherit the codes from the MMC driver where a FIXME was put in the comment. However the correct operation after read should be cache invalidate, not flush. The underlying drivers should be responsible for the cache operation. Remove these codes completely. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: York Sun <york.sun@nxp.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: York Sun <york.sun@nxp.com>
2017-09-14ARM: DRA7: Cleanup old pinctrl macrosSuman Anna
Commit 6ae4c3efbd62 ("ARM: DRA7: Add pinctrl register definitions") has added new macros for pinmux configuration in line with the kernel definitions. Cleanup the old pinctrl macros from the common header file so that they are not used by any new boards. Signed-off-by: Suman Anna <s-anna@ti.com>
2017-09-14ARM: at91: spl: Add macro CONFIG_XXXX_BOOT supportWenyou Yang
Use the CONFIG_XXXX_BOOT to indicate the boot media, instead of the CONFIG_SYS_USE_XXXX option, which is declared by CONFIG_SYS_EXTRA_OPTIONS option. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-09-14ARM: at91: Remove hardware.h included in configsWenyou Yang
As said in READRE.kconfig, include/configs/*.h will be removed after all options are switched to Kconfig. As the first step, remove the follow line from include/configs/*.h. #include <asm/hardware.h> Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-09-14ARM: at91: Add the SoC options to KconfigWenyou Yang
To prepare to remove the SoCs options such as SAMA5D2, SAMA5D3 and SAMA5D4 from the CONFIG_SYS_EXTRA_OPTIONS option which is deprecated, add the SoC options to Kconfig. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-09-14ARM: at91: Move CONFIG_AT91FAMILY option to KconfigWenyou Yang
Move the CONFIG_AT91FAMILY option from include/mach/<soc>.h header file to Kconfig. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-09-14board: atmel: Add SAMA5D27 SOM1 EK boardWenyou Yang
The SAMA5D27-SiP (System in Package) integrates the SAMA5D2 with 1Gbit DDR2-SDRAM in a single package. The SAMA5D27 SOM1 embeds a 64Mbit QSPI flash, KSZ8081 Phy and Mac-address EEPROM. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-14ARM: at91: Get the Chip ID of SAMA5D2 SiPWenyou Yang
The SAMA5D2 SiP(System in Package) has different Chip IDs in the CHIPID and CHIP_EXID registers. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-14ARM: at91: mach: Add missing defines of MPDDRCWenyou Yang
Add missing defines of Multiport DDR-SDRAM Controller (MPDDRC). Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-14ARM: at91: spl: Add boot device for boot from QSPIWenyou Yang
Add the boot device for booting from the QSPI flash. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-14ARM: at91: spl: Add mck function to lower rate while switchingWenyou Yang
Refer to the commit 70f8c8316ad(PMC: add new mck function to lower rate while switching) from AT91Bootstrap. While switching to a lower clock source, we must switch the clock source first instead of last. Otherwise, we could end up with too high frequency on internal bus and peripherals. This happens on SAMA5D2 as exitting from the ROM code. Add a function pmc_mck_init_down() to allow this sequence. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-14ARM: at91: spl: Adjust switching to oscillator for SAMA5D2Wenyou Yang
As said in 29.5.7 section of SAMA5D2 datasheet, before switching to the crystal oscillator, a check must be carried out to ensure that the oscillator is present and that its freqency is valid. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-14atmel: common: Add function to display via DM_VIDEO's APIWenyou Yang
Add a function to display the company's logo and board information via the API from DM_VIDEO. This function can be shared by other atmel boards, so locate it in board/atmel/common folder. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-14ARM: dts: at91: sama5: Add the sfr nodeWenyou Yang
For sama5d2, add the sfr node with syscon support. In order to access the SFR_UTMICKTRIM register for the utmi clock driver, add the phandle property for the utmi node to point to the sfr node. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-09-14clk: at91: utmi: Set the reference clock frequencyWenyou Yang
By default, it is assumed that the UTMI clock is generated from a 12 MHz reference clock (MAINCK). If it's not the case, the FREQ field of the SFR_UTMICKTRIM has to be updated to generate the UTMI clock in the proper way. The UTMI clock has a fixed rate of 480 MHz. In fact, there is no multiplier we can configure. The multiplier is managed internally, depending on the reference clock frequency, to achieve the target of 480 MHz. The patch is cloned from the patch of mailing-list: [PATCH v2] clk: at91: utmi: set the mainck rate Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> [trini: Depend on SPL_DM] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-13Convert CONFIG_EMIF4 et al to KconfigAdam Ford
This converts the following to Kconfig: CONFIG_EMIF4 CONFIG_SDRC Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-09-13arm: dts: omap3: Re-sync DTS files with Linux 4.13-RC5Adam Ford
The DTS files had some spacing issues and they needed fixing. This pull re-sync's the OMAP3xx related DTS files with Linux 4.13-RC5. To keep the DTS and DTSI files clean and in sync with Linux, new u-boot.dtsi files are added. Signed-off-by: Adam Ford <aford173@gmail.com> V3: The resync broke card detect on MMC1 on Logic PD's Torpedo, so we add the cd-invert to the Torpedo's -u-boot.dtsi file. V2: Add the u-boot.dtsi files for OMAP3, OMAP36xx, and Torpedo Remove the need for the second patch in the series
2017-09-13ARM: dts: ethernut5: Fix the build warningWenyou Yang
Fix the building warning as below: ---8<---- Warning (reg_format): "reg" property in /i2c-gpio-0/pcf8563@50 has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) Warning (avoid_default_addr_size): Relying on default #address-cells value for /i2c-gpio-0/pcf8563@50 Warning (avoid_default_addr_size): Relying on default #size-cells value for /i2c-gpio-0/pcf8563@50 --->8---- Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-12ARM: DRA72x: Add support for detection of DRA71x SR 2.1Vishal Mahaveer
DRA71x processors are reduced pin and software compatible derivative of DRA72 processors. Add support for detection of SR2.1 version of DRA71x family of processors. Signed-off-by: Vishal Mahaveer <vishalm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-09-12dma: import linux/dma-direction.h to consolidate enum dma_data_directionMasahiro Yamada
Import include/linux/dma-direction.h from Linux 4.13-rc7 and delete duplicated definitions of enum dma_data_direction. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
generated by cgit (git 2.34.1) at 2024-12-29 17:09:46 +0000