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2020-05-01imx: imx8m: add i.MX8MN variants supportPeng Fan
Add i.MX8MN variants support Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01imx: imx8m: add i.MX8MQ Dual and QuadLite supportPeng Fan
Add i.MX8MQ Dual and QuadLite variants. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01imx: cpu: support speed grade for i.MX8MPPeng Fan
i.MX8MP speed grade use same layout as i.MX8MN, so reuse it for i.MX8MP Reviewed-by: Ye Li <ye.li@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01imx8mn: Update speed gradePeng Fan
imx8mn speed grade fuse uses new definitions as below. So have to update get_cpu_speed_grade_hz function to match it. SPEED_GRADE[5:4] SPEED_GRADE[3:0] MHz xx 0000 2300 xx 0001 2200 xx 0010 2100 xx 0011 2000 xx 0100 1900 xx 0101 1800 xx 0110 1700 xx 0111 1600 xx 1000 1500 xx 1001 1400 xx 1010 1300 xx 1011 1200 xx 1100 1100 xx 1101 1000 xx 1110 900 xx 1111 800 Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-05-01imx8mm: Update CPU speed gradingYe Li
According to iMX8MM datasheet (IMX8MMIEC_Rev_D and IMX8MMCEC_Rev_D), the speed grading for imx8mm is 800Mhz, 1.2Ghz, 1.6Ghz and 1.8Ghz. Update them to get_cpu_speed_grade_hz function. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-05-01imx: fix cpu_type helperPeng Fan
i.MX8MP use 0x182 as its ID, so 0xff is not valid to get the cpu type, extend it to 0x1ff. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01ARM: imx: imx8mm: Add missing clock entries for FEC clockMarek Vasut
All the FEC ethernet clock entries for iMX8MM are missing, while they are already present on iMX8MQ. Fill in the nodes on iMX8MM, as the FEC ethernet gets bogus clock information otherwise which makes ethernet inoperable. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-05-01rockchip: rk3399: Add Nanopi M4 2GB board supportDeepak Das
commit b2f5da9dd068 ("rockchip: rk3399: Add Nanopi M4 board support") added support for Nanopi M4 board with Dual-Channel 4GB LPDDR3-1866 RAM. This patch adds another variant of NanoPi M4 board with Dual-Channel 2GB DDR3-1866 RAM. Signed-off-by: Deepak Das <deepakdas.linux@gmail.com>
2020-05-01rk3399: Add ROC-RK3399-PC Mezzanine boardSuniel Mahesh
Add Firefly ROC-RK3399-PC Mezzanine board which is an extension board on top of roc-rk3399-pc. Will drop the separate defconfig file, once we support the board detection at runtime. Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-01arm: dts: rk3399: Sync roc-pc-mezzanine from v5.7-rc1Jagan Teki
Sync Firefly ROC-RK3399-PC Mezzanine Board dts file from Linux v5.7-rc1. Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-01arm64: dts: rk3399: Sync v5.7-rc1 from LinuxJagan Teki
Sync rk3399 dts(i) files from v5.7-rc1 linux-next. Reason: To get updated PCIe nodes and properties on respective dts(i) files. Summary: - sync won't include new board dts(i) - sync will add required files used on respective dts(i) - rk3399-puma-u-boot.dtsi spiflash label changed to norflash - move puma.dtsi bios_enable into rk3399-puma-u-boot.dtsi - move legacy max-frequency of sdhci into rk3399-u-boot.dtsi - update cross-ec-[keyboard|sbs].dtsi path as per U-Boot - keep roc-rk3399-pc dc_12v changes to -u-boot.dtsi Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-01arm64: dts: rk3399-evb: Move u-boot properties into -u-boot.dtsiJagan Teki
Move U-Boot specific properties into rk3399-evb u-boot specific dtsi file. This would help to sync the devicetrees from Linux whenever required instead of adding specific nodes. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-01arm64: dts: rk3399-puma: Move u-boot properties into -u-boot.dtsiJagan Teki
Move U-Boot specific properties into rk3399-puma u-boot specific dtsi file. This would help to sync the devicetrees from Linux whenever required instead of adding specific nodes. Cc: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-01rockchip: dts: rock64: Fix XHCI usageChen-Yu Tsai
If the VBUS regulator is always-on, XHCI will fail to detect USB 3.0 devices; USB 2.0 devices will work however. Make the VBUS regulator controllable and tie it to only the XHCI. This makes all three USB ports usable. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-01rockchip: rk3328: Add support for ROC-RK3328-CC boardChen-Yu Tsai
The ROC-RK3328-CC from Firefly and Libre Computer Project is a credit card size development board based on the Rockchip RK3328 SoC, with: - 1/2/4 GB DDR4 DRAM - eMMC connector for optional module - micro SD card slot - 1 x USB 3.0 host port - 2 x USB 2.0 host port - 1 x USB 2.0 OTG port - HDMI video output - TRRS connector with audio and composite video output - gigabit Ethernet - consumer IR receiver - debug UART pins The ROC-RK3328-CC has the enable pin of the SD card power switch tied to GPIO_0_D6. This pin also has the function SDMMC0_PWREN, which is muxed by default. SDMMC0_PWREN is an active high signal controlled by the MMC controller, however the switch enable is active low, and pulled low (enabled) by default to make things work on boot. As such, we need to mux away from SDMMC0_PWREN and use GPIO to enable power to the card. The default GPIO state for the pin is pull-down and input, which doesn't require extra configuration when paired with the external pull-down and active low switch. Deal with this by enabling regulator support in SPL, and setting "u-boot,dm-spl" for the regulator and other device nodes needed for muxing the pin. The device tree file is synced from the Linux kernel next-20200324. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-01rockchip: dts: rk3328: Sync device tree files from LinuxChen-Yu Tsai
This syncs rk3328 device tree files from the Linux kernel next-20200324. The last commit to touch these files is: b2411befed60 ("arm64: dts: add bus to rockchip amba nodenames") Additional changes not yet in the Linux kernel include: arm64: dts: rockchip: rk3328: drop #address-cells, #size-cells from grf node arm64: dts: rockchip: rk3328: drop non-existent gmac2phy pinmux options arm64: dts: rockchip: rk3328: Replace RK805 PMIC node name with "pmic" Changes include: - conversion of raw pin numbers to macros - removal of deprecated RK_FUNC_* macros - update of device tree binding headers - new devices - device tree cleanups - gmac2phy disabled in -u-boot.dtsi as it is not supported in U-boot This includes a re-ordering of the USB device nodes compared to upstream Linux, moving the dwc2 OTG controller after the EHCI/OHCI nodes. This is currently required as otherwise the dwc2 controller would not be able to detect devices in some cases. This may be due to lack of USB PHY support in U-boot. Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2020-05-01rockchip: dts: rk3328: Move OTG node's hnp-srp-disable to rk3328-u-boot.dtsiChen-Yu Tsai
The "hnp-srp-disable" property for dwc2 is specific to U-boot, not part of upstream Linux's device tree bindings. Move it to rk3328-u-boot.dtsi to avoid losing it when syncing device tree files. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-01rockchip: dts: rk3328-evb: Move gmac2io related nodes to -u-boot.dtsiChen-Yu Tsai
The device tree file for rk3328-evb in the Linux kernel does not have gmac2io enabled. Instead, gmac2phy is enabled, but that is not supported in U-boot. Move the gmac2io related nodes to rk3328-evb-u-boot.dtsi to preserve the current functionality. When the device tree files are synced, gmac2phy should be marked as "broken" in -u-boot.dtsi files. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Loic Devulder <ldevulder@suse.com> Tested-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2020-05-01rockchip: dts: rk3328-evb: Move vcc5v0-host-xhci-drv to -u-boot.dtsiChen-Yu Tsai
USB 3.0 is only supported in U-boot, not in the Linux kernel where the device tree files are ultimately synced from. While the xhci node was moved, the external vbus regulator was not. Move it as well. Fixes: 2e91e2025c1b ("rockchip: rk3328: migrate u-boot node to -u-boot.dtsi") Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Loic Devulder <ldevulder@suse.com> Tested-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2020-04-30Merge https://gitlab.denx.de/u-boot/custodians/u-boot-spiTom Rini
- distro boot support for SPI flash - sifive spi flash driver
2020-04-30sifive: fu540: Enable spi-nor flash supportJagan Teki
HiFive Unleashed A00 support is25wp256 spi-nor flash, So enable the same and add test result log for future reference. Tested on SiFive FU540 board. Thanks to Sagar for various use cases and tests. [QUAD mode in dt with spi-tx-bus-width: <4>] pp opcode = 0x34 [QUAD MODE] read opcode = 0x6c [QUAD MODE] erase opcode = 0x21 SPI-NOR: 1. erase entire flash: Pass 2. write entire flash: Pass 3. read entire flash: Pass 4. cmp 32MiB read back data: Pass 5. MMC: Booted Linux and dtb from mmc [SPI MODE in dt with spi-tx-bus-width: <1>] pp opcode = 0x12 [SPI MODE] read opcode = 0xc [SPI MODE] erase opcode = 0x21 SPI-NOR: 1. erase entire flash: Pass 2. write entire flash: Pass 3. read entire flash: Pass 4. cmp 32MiB read back data: Pass 5. MMC: Booted Linux and dtb from mmc Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
2020-04-30riscv: dts: hifive-unleashed-a00: Add -u-boot.dtsiJagan Teki
Add U-Boot specific dts file for hifive-unleashed-a00, this would help to add u-boot specific properties and other node changes without touching the base dts(i) files which are easy to sync from Linux. Added spi2 alias for qspi2 as an initial u-boot specific property change. spi probing in current dm model is very much rely on aliases numbering. Even though the qspi2 can't come under any associated spi nor flash it would require to specify the same to make proper binding happen for other spi slaves. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
2020-04-30Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86Tom Rini
- DM ACPI support (Part A) - Improve support for chain-loading x86 U-Boot
2020-04-30Merge tag 'xilinx-for-v2020.07-rc2' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2020.07-rc2 mmc: - Fix dt property handling via generic function clk: - Fix versal watchdog clock setting nand: - Fix zynq nand command comparison xilinx: - Enable ubifs - Sync board_late_init configurations with initrd_high setup - Make custom distro boot more verbose zynq: - Kconfig alignments - Fix nand cse configuration zynqmp: - Fix zcu104 low level qspi configuration - Small DT updates Signed-off-by: Tom Rini <trini@konsulko.com>
2020-04-30Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini
- Add DM_ETH support for DPAA1, DPAA2 based RDB platforms: ls1046ardb, ls1043ardb, lx2160ardb, ls2088ardb, ls1088ardb. - Add GICv3 support for ls1028a, ls2088a, ls1088a. - Add lpuart support on ls1028aqds. - Few bug fixes and updates on ls2088a, ls1012a, ls1046a, ls1021a based platforms.
2020-04-30x86: Use the existing stack when chain-loadingSimon Glass
With chromebook_coral we normally run TPL->SPL->U-Boot. This is the 'bare metal' case. When running from coreboot we put u-boot.bin in the RW_LEGACY portion of the image, e.g. with: cbfstool image-coral.serial.bin add-flat-binary -r RW_LEGACY \ -f /tmp/b/chromebook_coral/u-boot.bin -n altfw/u-boot \ -c lzma -l 0x1110000 -e 0x1110000 In this case U-Boot is run from coreboot (actually Depthcharge, its payload) so we cannot access CAR. Use the existing stack instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30x86: Add a way to detect running from corebootSimon Glass
If U-Boot is running from coreboot we need to skip low-level init. Add an way to detect this and to set the gd flag. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30x86: Move coreboot-table detection into common codeSimon Glass
To support detecting booting from coreboot, move the code which locates the coreboot tables into a common place. Adjust the algorithm slightly to use a word comparison instead of string, since it is faster. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the comments to 960KB] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30x86: cpu: Skip init code when chain loadingSimon Glass
When U-Boot is not the first-stage bootloader the interrupt and cache init must be skipped, as well as init for various peripherals. Update the code to add checks for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30x86: apl: Skip init code when chain loadingSimon Glass
When U-Boot is not the first-stage bootloader the FSP-S init must be skipped. Update it to add a check. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30x86: fsp: Allow skipping init code when chain loadingSimon Glass
It is useful to be able to boot the same x86 image on a device with or without a first-stage bootloader. For example, with chromebook_coral, it is helpful for testing to be able to boot the same U-Boot (complete with FSP) on bare metal and from coreboot. It allows checking of things like CPU speed, comparing registers, ACPI tables and the like. When U-Boot is not the first-stage bootloader much of this code is not needed and can break booting. Add checks for this to the FSP code. Rather than checking for the amount of available SDRAM, just use 1GB in this situation, which should be safe. Using 2GB may run into a memory hole on some SoCs. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30acpi: Add an acpi commandSimon Glass
It is useful to dump ACPI tables in U-Boot to see what has been generated. Add a command to handle this. To allow the command to find the tables, add a position into the global data. Support subcommands to list and dump the tables. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-04-30acpi: Put table-setup code in its own functionSimon Glass
We always write three basic tables to ACPI at the start. Move this into its own function, along with acpi_fill_header(), so we can write a test for this code. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-30acpi: Move acpi_add_table() to generic codeSimon Glass
Move this code to a generic location so that we can test it with sandbox. This requires adding a few new fields to acpi_ctx, so drop the local variables used in the original code. Also use mapmem to avoid pointer-to-address casts which don't work on sandbox. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-04-30acpi: Drop code for missing XSDT from acpi_write_rsdp()Simon Glass
We don't actually support tables without an XSDT so we can drop this dead code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-04-30x86: Allow devices to write ACPI tablesSimon Glass
Call the new core function to permit devices to write their own ACPI tables. These tables will appear after all other tables. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-04-30acpi: Convert part of acpi_table to use acpi_ctxSimon Glass
The current code uses an address but a pointer would result in fewer casts. Also it repeats the alignment code in a lot of places so this would be better done in a helper function. Update write_acpi_tables() to make use of the new acpi_ctx structure, adding a few helpers to clean things up. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-04-30acpi: Add a method to write tables for a deviceSimon Glass
A device may want to write out ACPI tables to describe itself to Linux. Add a method to permit this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-04-29Merge https://gitlab.denx.de/u-boot/custodians/u-boot-shTom Rini
- rmobile gen2/gen3 DTS sync and defconfig consolidation
2020-04-29driver: net: fm: add DM ETH supportMadalin Bucur
Probe the FMan MACs based on the device tree while retaining the legacy code/functionality. One notable change introduced here is that, for DM_ETH, the name of the interfaces is corrected to the fmX-macY format, that avoids the referral to the MAC block names which were incorrect for FMan v3 devices (i.e. DTSEC, TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1). The legacy code is left unchanged in this respect. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-29ARM: dts: add QorIQ DPAA 1 FMan v3 to LS1046ARDBMadalin Bucur
Introduce the QorIQ DPAA 1 Frame Manager nodes in the LS1046ARDB device tree. The device tree fragments are copied over with little modification from the Linux kernel source code. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-29ARM: dts: add QorIQ DPAA 1 FMan v3 for LS1046AMadalin Bucur
Add the QorIQ DPAA 1 Frame Manager v3 device tree nodes for the LS1046A SoC. The device tree fragments are copied over with little modification from the Linux kernel source code. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-29ARM: dts: add QorIQ DPAA 1 FMan v3 to LS1043ARDBMadalin Bucur
Introduce the QorIQ DPAA 1 Frame Manager nodes in the LS1043ARDB device tree. The device tree fragments are copied over with little modification from the Linux kernel source code. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-29ARM: dts: add QorIQ DPAA 1 FMan v3 for LS1043AMadalin Bucur
Add the QorIQ DPAA 1 Frame Manager v3 device tree nodes for the LS1043A SoC. The device tree fragments are copied over with little modification from the Linux kernel source code. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-29ARM: dts: add QorIQ DPAA 1 FMan v3 device tree nodesMadalin Bucur
Add the QorIQ DPAA Frame Manager v3 device tree nodes description. The device tree fragments are copied over with little modification from the Linux kernel source code. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-29armv8: ls1028aqds: add lpuart dts supportYuantian Tang
Rename fsl-ls1028a-qds.dts to fsl-ls1028a-qds.dtsi so that it can be used as common device tree for lpuart and duart. Add lpuart device tree and duart device tree respectively for qds which are used with duart and lpuart console. Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Yuantian Tang <andy.tang@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-29arm: dts: ls1028a: add lpuart nodesYuantian Tang
Add lpuart nodes to enable lpuart feature Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Yuantian Tang <andy.tang@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-29arm: dts: ls1088ardb: add DPMAC and PHY nodesIoana Ciornei
In order to maintain compatibility with the Linux DTS, the entire fsl-mc node is added but instead of being probed by a dedicated bus driver it will be a simple-mfd. Also, annotate the external MDIO nodes and describe the PHYs (8 x VSC8514, AQR105). Also, add phy-handles for the dpmacs to their associated PHY. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-29arm: dts: ls2088ardb: add DPMAC and PHY nodesIoana Ciornei
In order to maintain compatibility with the Linux DTS, the entire fsl-mc node is added but instead of being probed by a dedicated bus driver it will be a simple-mfd. Also, annotate the external MDIO nodes and describe the PHYs (4 x AQR405 and 4 x CS4340). Also, add phy-handles for the dpmacs to their associated PHY. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-29arm: dts: lx2160ardb: add DPMAC and PHY nodesIoana Ciornei
In order to maintain compatibility with the Linux DTS, the entire fsl-mc node is added but instead of being probed by a dedicated bus driver it will be a simple-mfd. Also, annotate the EMDIO1 node and describe the 2 AR8035 RGMII PHYs and the 2 AQR107 PHYs. Also, add phy-handles for the dpmacs to their associated PHY. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
generated by cgit (git 2.34.1) at 2025-02-02 06:03:41 +0000