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add reset controller status register
Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Bo Shen <voice.shen@atmel.com>
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if CONFIG_AT91SAM9_WATCHDOG is set, do not disable WDT in
SPL
Signed-off-by: Heiko Schocher <hs@denx.de>
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As the at91cap9adk board is removed by commit: b5508344
(ARM: remove broken "at91cap9adk" board), so the at91cap9
code is not used anymore, and also the document for
at91cap9 can not be found on www.atmel.com, so remove the
at91cap9 related code.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
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Signed-off-by: Bo Shen <voice.shen@atmel.com>
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The sama5d4ek support boot up from NAND flash, SD/MMC card and
also the SPI flash.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
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Signed-off-by: Bo Shen <voice.shen@atmel.com>
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The SAMAA5D4 SoC can access DDR in interleave mode.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
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Signed-off-by: Bo Shen <voice.shen@atmel.com>
[fix subject]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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Signed-off-by: Bo Shen <voice.shen@atmel.com>
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Signed-off-by: Bo Shen <voice.shen@atmel.com>
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The SAMA5D4 SoC on chip rc oscillator can not be disabled.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
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Some SoC need to redirect the saic to aic to make the interrupt to
work, here add a weak function to be replaced by real function.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
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Some SoC need to configure the bus matrix, add an weak function
to be replace by real function.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
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The SFR (special function registers) can be shared bwteen
sama5d3 and sama5d4 soc.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
[whitespace adoptions for 80 char compliance]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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This matrix header file can be shared between sama5d3 and sama5d4 soc.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
[whitespace adaptions for 80 char compliance]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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Signed-off-by: Bo Shen <voice.shen@atmel.com>
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It turns out that the device_mode_data is rsb specific, rather then slave
specific, so integrate the rsb_set_device_mode() call into rsb_init().
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
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Add support for the A80 to the rsb code.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
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And use this to set the GMAC Transmit Clock Delay Chain value on Banana
boards, rather then keying of CONFIG_TARGET_FOO.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
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It is painful to specify the full path to the device tree with the -d
option. It is normally kept in the same directory as U-Boot, so provide
an option to use this by default.
Signed-off-by: Simon Glass <sjg@chromium.org>
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The other boards got updated to the standard binding. Update sandbox as
well.
Signed-off-by: Simon Glass <sjg@chromium.org>
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SCTLR is the abbreviation of System Control Register, so we should
use SCTLR but not SCTRL.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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The Juno Development Platform is a physical Versatile Express
device with some differences from the emulated semihosting
models. The main difference is that the system is split in
a SoC and an FPGA where the SoC hosts the serial ports at
totally different adresses.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The Versatile Express ARMv8 semihosted FVP platform is still
using the legacy CONFIG_SYS_EXTRA_OPTIONS method to configure
some compile-time flags. Get rid of this and create a Kconfig
entry for the FVP model, and a selectable bool for the
semihosting library.
The FVP subboard is now modeled as a target choice so we can
eventually choose between different ARMv8 versatile express
boards (FVP, base model, Juno...) this way. All dependent
symbols are updated to reflect this.
The 64bit Versatile Express board symbols are renamed
VEXPRESS64 so we have some chance to see what is actually
going on. Tested on the FVP fast model.
Acked-by: Steve Rae <srae@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Unify and move code in arch/mips/cpu/mips[32|64]/ to arch/mips/cpu/.
The CPU specific config.mk files need to remain until
CONFIG_STANDALONE_LOAD_ADDR is converted to a global Kconfig symbol.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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Move all au1x00 code out of arch/mips/cpu/mips32 to allow
unification of CPU code in a later patch. The reorganization
of the SoC specific header files will be done in a later patch
series.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Paul Burton <paul.burton@imgtec.com>
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In preparation for sharing a single copy of start.S between mips32 &
mips64, handle setting the KX bit of the cop0 Status register when the
mips32 start.S is built for mips64.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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In preparation for sharing a single copy of start.S between mips32 &
mips64, handle mips64 relocations in the mips32 start.S when built for
mips64.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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Where the mips32 & mips64 implementations of start.S differ in terms of
access sizes & offsets, use the appropriate macros from asm.h to
abstract those differences away. This is in preparation for sharing a
single copy of start.S between mips32 & mips64.
The exception to this is loads of immediates to be written to the cop0
Config register, which is a 32bit register on mips64 and therefore
constants written to it can be loaded as such.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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The EC has no concept of offset, so use a value of 0.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This change fixes i2c bus numbering for Odroid U3.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
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Some versions of Exynos5 supports High-Speed I2C,
on few interfaces, this change allows support this.
The new flag is: PINMUX_FLAG_HS_MODE
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Akshay Saraswat <akshay.s@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
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Without this alias setting, the seq numbers
of the i2c devices are wrong.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
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This patch modify i2c nodes in exynos4.dtsi with:
- adding proper interrupts arrays for each i2c node,
which allows to decode periph id
- add reg address for each i2c node for i2c driver internal use
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
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this is an atempt to make the export of functions typesafe.
I replaced the jumptable void ** by a struct (jt_funcs) with function pointers.
The EXPORT_FUNC macro now has 3 fixed parameters and one
variadic parameter
The first is the name of the exported function,
the rest of the parameters are used to format a functionpointer
in the jumptable,
the EXPORT_FUNC macros are expanded three times,
1. to declare the members of the struct
2. to initialize the structmember pointers
3. to call the functions in stubs.c
Signed-off-by: Martin Dorwig <dorwig@tetronik.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
(resending to the list since my tweaks are not quite trivial)
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Rather than assuming that the chip offset length is 1, allow it to be
provided. This allows chips that don't use the default offset length to
be used (at present they are only supported by the command line 'i2c'
command which sets the offset length explicitly).
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
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U-Boot now supports using GPIOs using bank phandles instead of global
numbers. Update the exynos device tree files to use this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
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This new method is much easier and matches the kernel.
Signed-off-by: Simon Glass <sjg@chromium.org>
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These functions are going away, so use the new uclass support instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
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These functions serve no useful purpose, and conflict with the generic API.
Drop them.
Signed-off-by: Simon Glass <sjg@chromium.org>
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These functions are going away, so use the new uclass support instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Add a new 'demo light' command which uses GPIOs to control imaginary lights.
Each light is assigned a bit number in the overall value. This provides an
example driver for using the new GPIO API.
Signed-off-by: Simon Glass <sjg@chromium.org>
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In f0c3a6c we stopped setting gd in board_init_f, but later had to
revert to due problems on certain platforms. As davinci does not look
to have these problems, we can drop the setting here and rely upon
crt0.S to do it.
Cc: Peter Howard <pjh@northern-ridge.com.au>
Signed-off-by: Tom Rini <trini@ti.com>
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Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
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Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
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