summaryrefslogtreecommitdiff
path: root/arch
AgeCommit message (Collapse)Author
2013-10-14Coding Style cleanup: drop some excessive empty linesWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2013-10-14Coding Style cleanup: remove trailing empty linesWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2013-10-14Coding Style cleanup: replace leading SPACEs by TABsWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Drop changes for PEP 4 following python tools] Signed-off-by: Tom Rini <trini@ti.com>
2013-10-14Coding Style cleanup: remove trailing white spaceWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2013-10-14ARM: omap4-panda: Add MAC address creation for pandaDan Murphy
Add a MAC address create based on the OMAP die ID registers. Then poplulate the ethaddr enviroment variable so that the device tree alias can be updated prior to boot. Signed-off-by: Dan Murphy <dmurphy@ti.com>
2013-10-14ARM: omap4: Update sdram setting for panda rev A6Dan Murphy
OMAP4 panda rev A6 is a 4430 es2.3 IC with an updated memory part. The panda rev A6 uses Elpida 2x4Gb memory and no longer uses Micron so the timings needs to be updated Signed-off-by: Dan Murphy <dmurphy@ti.com>
2013-10-08Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini
2013-10-08Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini
2013-10-08spi: exynos: Support word transfersRajeshwari Shinde
Since SPI register access is so expensive, it is worth transferring data a word at a time if we can. This complicates the driver unfortunately. Use the byte-swapping feature to avoid having to convert to/from big endian in software. This change increases speed from about 2MB/s to about 4.5MB/s. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2013-10-07socfpga: Adding System Manager driverChin Liang See
Adding System Manager driver which will configure the pin mux for real hardware Cyclone V development kit (not Virtual Platform) Signed-off-by: Chin Liang See <clsee@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> Acked-by: Dinh Nguyen <dinguyen@altera.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
2013-10-07omap1510inn: arm925t: remove supportAlbert ARIBAUD
omap1510inn is orphan and has been for years now. Reove it and, as it was the only arm925t target, also remove arm925t support. Update doc/README.scrapyard accordingly. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-10-07armv7: hw_data: change clock divider setting.Poddar, Sourav
Clock requirement for qspi clk is 192 Mhz. According to the below formulae, f dpll = f ref * 2 * m /(n + 1) clockoutx2_Hmn = f dpll / (hmn+ 1) fref = 20 Mhz, m = 96, n = 4 gives f dpll = 768 Mhz For clockoutx2_Hmn to be 768, hmn + 1 should be 4. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2013-10-07omap5: add qspi supportMatt Porter
Add QSPI definitions and clock configuration support. Signed-off-by: Matt Porter <matt.porter@linaro.org> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2013-10-07ARM: virtualization: replace verbose license with SPDX identifierAndre Przywara
The original creation of arch/arm/cpu/armv7/{virt-v7.c,nonsec_virt.S} predates the SPDX conversion, so the original elaborate license statements sneaked in. Fix this by replacing them with the proper abbreviation. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-10-07ARM: IGEP0033: Update timing to run DDR at 400MHz.Enric Balletbo i Serra
We can run the DDR at 400MHz, so update the timings for that purpose. Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com> Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
2013-10-04Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini
2013-10-03ARM: extend non-secure switch to also go into HYP modeAndre Przywara
For the KVM and XEN hypervisors to be usable, we need to enter the kernel in HYP mode. Now that we already are in non-secure state, HYP mode switching is within short reach. While doing the non-secure switch, we have to enable the HVC instruction and setup the HYP mode HVBAR (while still secure). The actual switch is done by dropping back from a HYP mode handler without actually leaving HYP mode, so we introduce a new handler routine in our new secure exception vector table. In the assembly switching routine we save and restore the banked LR and SP registers around the hypercall to do the actual HYP mode switch. The C routine first checks whether we are in HYP mode already and also whether the virtualization extensions are available. It also checks whether the HYP mode switch was finally successful. The bootm command part only calls the new function after the non-secure switch. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-10-03ARM: add SMP support for non-secure switchAndre Przywara
Currently the non-secure switch is only done for the boot processor. To enable full SMP support, we have to switch all secondary cores into non-secure state also. So we add an entry point for secondary CPUs coming out of low-power state and make sure we put them into WFI again after having switched to non-secure state. For this we acknowledge and EOI the wake-up IPI, then go into WFI. Once being kicked out of it later, we sanity check that the start address has actually been changed (since another attempt to switch to non-secure would block the core) and jump to the new address. The actual CPU kick is done by sending an inter-processor interrupt via the GIC to all CPU interfaces except the requesting processor. The secondary cores will then setup their respective GIC CPU interface. While this approach is pretty universal across several ARMv7 boards, we make this function weak in case someone needs to tweak this for a specific board. The way of setting the secondary's start address is board specific, but mostly different only in the actual SMP pen address, so we also provide a weak default implementation and just depend on the proper address to be set in the config file. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-10-03ARM: trigger non-secure state switch during bootm executionAndre Przywara
To actually trigger the non-secure switch we just implemented, call the switching routine from within the bootm command implementation. This way we automatically enable this feature without further user intervention. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-10-03ARM: add C function to switch to non-secure stateAndre Przywara
The core specific part of the work is done in the assembly routine in nonsec_virt.S, introduced with the previous patch, but for the full glory we need to setup the GIC distributor interface once for the whole system, which is done in C here. The routine is placed in arch/arm/cpu/armv7 to allow easy access from other ARMv7 boards. We check the availability of the security extensions first. Since we need a safe way to access the GIC, we use the PERIPHBASE registers on Cortex-A15 and A7 CPUs and do some sanity checks. Boards not implementing the CBAR can override this value via a configuration file variable. Then we actually do the GIC enablement: a) enable the GIC distributor, both for non-secure and secure state (GICD_CTLR[1:0] = 11b) b) allow all interrupts to be handled from non-secure state (GICD_IGROUPRn = 0xFFFFFFFF) The core specific GIC setup is then done in the assembly routine. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-10-03ARM: add assembly routine to switch to non-secure stateAndre Przywara
While actually switching to non-secure state is one thing, another part of this process is to make sure that we still have full access to the interrupt controller (GIC). The GIC is fully aware of secure vs. non-secure state, some registers are banked, others may be configured to be accessible from secure state only. To be as generic as possible, we get the GIC memory mapped address based on the PERIPHBASE value in the CBAR register. Since this register is not architecturally defined, we check the MIDR before to be from an A15 or A7. For CPUs not having the CBAR or boards with wrong information herein we allow providing the base address as a configuration variable. Now that we know the GIC address, we: a) allow private interrupts to be delivered to the core (GICD_IGROUPR0 = 0xFFFFFFFF) b) enable the CPU interface (GICC_CTLR[0] = 1) c) set the priority filter to allow non-secure interrupts (GICC_PMR = 0xFF) Also we allow access to all coprocessor interfaces from non-secure state by writing the appropriate bits in the NSACR register. The generic timer base frequency register is only accessible from secure state, so we have to program it now. Actually this should be done from primary firmware before, but some boards seems to omit this, so if needed we do this here with a board specific value. The Versatile Express board does not need this, so we remove the frequency from the configuration file here. After having switched to non-secure state, we also enable the non-secure GIC CPU interface, since this register is banked. Since we need to call this routine also directly from the smp_pen later (where we don't have any stack), we can only use caller saved registers r0-r3 and r12 to not mess with the compiler. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-10-03ARM: add secure monitor handler to switch to non-secure stateAndre Przywara
A prerequisite for using virtualization is to be in HYP mode, which requires the CPU to be in non-secure state first. Add a new file in arch/arm/cpu/armv7 to hold a monitor handler routine which switches the CPU to non-secure state by setting the NS and associated bits. According to the ARM architecture reference manual this should not be done in SVC mode, so we have to setup a SMC handler for this. We create a new vector table to avoid interference with other boards. The MVBAR register will be programmed later just before the smc call. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-10-03ARM: prepare armv7.h to be included from assembly sourceAndre Przywara
armv7.h contains some useful constants, but also C prototypes. To include it also in assembly files, protect the non-assembly part appropriately. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-10-02Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini
2013-10-02Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD
2013-10-02Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD
2013-09-27i.MX6DQ/DLS: Add pad MX6_PAD_GPIO_1__USB_OTG_IDEric Nelson
This patch adds the pad to i.MX6DQ and changes the i.MX6DLS declaration to match the Linux kernel declaration. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de>
2013-09-27mx6: Fix use of improper value in enable_ipu_clockPierre Aubert
The value MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET that was used to initialize the CCGR3 register caused an undefined value for CG0. Signed-off-by: Pierre Aubert <p.aubert@staubli.com> CC: Stefano Babic <sbabic@denx.de> Acked-by: Eric Nelson <eric.nelson@boundarydevices.com>
2013-09-24ARM: atmel: add RNDIS gadget supportBo Shen
Add RNDIS gadget support to test atmel usba udc driver Signed-off-by: Bo Shen <voice.shen@atmel.com>
2013-09-24ARM: atmel: correct UDPHS nameBo Shen
Correct the UDPHS name from UDHPS Signed-off-by: Bo Shen <voice.shen@atmel.com> Acked-by: Marek Vasut <marex@denx.de>
2013-09-24USB: gadget: add atmel usba udc driverBo Shen
Add atmel usba udc driver support, porting from Linux kernel The original code in Linux Kernel information is as following commit e01ee9f509a927158f670408b41127d4166db1c7 Author: Jingoo Han <jg1.han@samsung.com> Date: Tue Jul 30 17:00:51 2013 +0900 usb: gadget: use dev_get_platdata() Use the wrapper function for retrieving the platform data instead of accessing dev->platform_data directly. Signed-off-by: Bo Shen <voice.shen@atmel.com>
2013-09-24Sound: I2S: Replacing I2S1 with I2S0 channel.Dani Krishna Mohan
This patch makes required changes to make use of I2S0 channel instead of I2S1 channel on exynos5250. Signed-off-by: Dani Krishna Mohan <krishna.md@samsung.com>
2013-09-24ARM: Added I2S0 clocks for audioDani Krishna Mohan
This patch makes the necessary changes for making use of I2S0 channel instead of I2S1 channel on smdk board. This changes are done to maintain the uniformity to use I2S0 channel. Signed-off-by: Dani Krishna Mohan <krishna.md@samsung.com>
2013-09-24DTS: Addition of I2S0 channel and replacing I2S1Dani Krishna Mohan
This patch enables default I2S0 channel.And I2S platform parameter has been moved to a common file viz exynos5.dtsi. Signed-off-by: Dani Krishna Mohan <krishna.md@samsung.com>
2013-09-23ARM: use r9 for gdJeroen Hofstee
To be more EABI compliant and as a preparation for building with clang, use the platform-specific r9 register for gd instead of r8. note: The FIQ is not updated since it is not used in u-boot, and under discussion for the time being. The following checkpatch warning is ignored: WARNING: Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-09-23ARM,relocate: do not use r9Jeroen Hofstee
r9 is a platform-specific register in ARM EABI and not per definition a general purpose register. Do not use it while relocating so it can be used for gd. cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2013-09-23ARM: refactor compiler options in config.mkMasahiro Yamada
Every ARM cpu config.mk (arch/arm/cpu/{CPUDIR}/config.mk) defines: PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float So, this patch moves the common compiler options to arch/arm/config.mk. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-09-23arm: zynq: Fix timer loadaddressMichal Simek
Reload address was written to the counter register instead of load register. The problem happens when timer expires but never reload to ~0UL (it is downcount timer). Reported-by: Stephen MacMahon <stephenm@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-09-23arm: prevent using movt/movw address loadsJeroen Hofstee
The movt/movw instruction can be used to hardcode an memory location in the instruction itself. The linker starts complaining about this if the compiler decides to do so: "relocation R_ARM_MOVW_ABS_NC against `a local symbol' can not be used" and it is not support by U-boot as well. Prevent their use by requiring word relocations. This allows u-boot to be build at other optimalization levels then -Os. Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> Cc: TigerLiu@viatech.com.cn Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Simon Glass <sjg@chromium.org>
2013-09-20ARM: OMAP5: Avoid writing into LDO SRAM bitsLokesh Vutla
Writing magic bits into LDO SRAM was suggested only for OMAP5432 ES1.0. Now these are no longer applicable. Moreover these bits should not be overwritten as they are loaded from EFUSE. So avoid writing into these registers. Boot tested on OMAP5432 ES2.0 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-09-20am335x:Handle worst case scenario for Errata 1.0.24Steve Kipisz
In Errata 1.0.24, if the board is running at OPP50 and has a warm reset, the boot ROM sets the frequencies for OPP100. This patch attempts to drop the frequencies back to OPP50 as soon as possible in the SPL. Then later the voltages and frequencies up set higher. Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com> Cc: Lars Poeschel <poeschel@lemonage.de> Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> [trini: Adapt to current framework] Signed-off-by: Tom Rini <trini@ti.com>
2013-09-20am335x_evm: am33xx_spl_board_init function and scale core frequencyTom Rini
Add a am33xx_spl_board_init (and enable the PMICs) that we may see, depending on the board we are running on. In all cases, we see if we can rely on the efuse_sma register to tell us the maximum speed. In the case of Beaglebone White, we need to make sure we are on AC power, and are on later than rev A1, and then we can ramp up to the PG1.0 maximum of 720Mhz. In the case of Beaglebone Black, we are either on PG2.0 that supports 1GHz or PG2.1. As PG2.0 may or may not have efuse_sma set, we cannot rely on this probe. In the case of the GP EVM, EVM SK and IDK we need to rely on the efuse_sma if we are on PG2.1, and the defaults for PG1.0/2.0. Signed-off-by: Tom Rini <trini@ti.com>
2013-09-20i.MX6DL/S: add drive-strength back to pads DISP0_DAT2/DAT10Eric Nelson
This patch fixes a regression introduced by commit 87d720e0. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
2013-09-20mx6slevk: Add Ethernet supportFabio Estevam
mx6slevk has a SMSC8720 connected in RMII mode. Add support for it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-09-20ARM: arch-mx6: fix PLL2_PFD2_FREQMarkus Niebel
according to the manual frequency of PLL2 PFD2 is 396.000.000 instead of 400.000.000 Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de> Acked-by: Stefano Babic <sbabic@denx.de>
2013-09-20am33xx: Add the efuse_sma CONTROL_MODULE registerTom Rini
Starting with PG2.1 we have a register in the CONTROL_MODULE that is set with the package type and maximum supported frequency. Add this, and the relevant mask/values. Signed-off-by: Tom Rini <trini@ti.com>
2013-09-20am33xx: Add am33xx_spl_board_init function, callTom Rini
We need to allow for a further call-out in spl_board_init. Call this am33xx_spl_board_init and add a __weak version. This function may be used to scale the MPU frequency up, depending on board needs. Signed-off-by: Tom Rini <trini@ti.com>
2013-09-20SPDX: fix IBM-pibs license identifierWolfgang Denk
The SPDX License List version 1.19 now contains an official entry for the IBM-pibs license. However, instead of our suggestion "ibm-pibs", the SPDX License List uses "IBM-pibs", with the following rationale: "The reason being that all other SPDX License List short identifiers tend towards using capital letters unless spelling a word. I'd prefer to be consistent to this end". Change the license IDs to use the official name. Signed-off-by: Wolfgang Denk <wd@denx.de>
2013-09-20arm: omap5: echi: Add GPL-2.0+ SPDX-License-IdentifierNobuhiro Iwamatsu
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2013-09-20Cosmetic: Fix a number of typos, no functional changes.Robert P. J. Day
Fix various misspellings of things like "environment", "kernel", "default" and "volatile", and throw in a couple grammar fixes. Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>