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2019-10-14Merge tag 'u-boot-imx-20191014' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20191014 ------------------- Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/597498628 - logicpd pinmux - i.MX7ULP: imx_ddr_size - fixes Toradex i.MX6/i.MX7 - pico-imx7d - tpc70 converted to DM - New Board: meerkat96 - add HAB version command - i.MX8 : imx8: Jump from alias to OCRAM address at SPL init imx8qm/qxp: Set SPL TEXT base to OCRAM base
2019-10-14Merge tag 'video-for-2020.01' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-video - panel bridge support in stm32 ltdc - DSI host uclass - sandbox DSI host uclass test driver and DSI host test - MIPI DSI helpers - Synopsys Designware MIPI DSI host bridge driver - STM32 DSI controller driver - OTM800A and RM68200 panel support - DSI host updates for stm32f769 and stm32mp1 dtsi files - splash screen for stm32f769 and stm32mp1 boards - stm32 defconfig updates for display support
2019-10-14Merge tag 'mmc-10-10-2019' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-mmc - Add sdhci driver for Broadcom iProc platform - Add a driver callback for power-cycle for mmc - Implement host_power_cycle callback for stm32_sdmmc2 - spl: dm_mmc: Initialize only the required mmc device
2019-10-14imx :hab: Add hab version commandSjoerd Simons
THe RVT data includes a major and minor version in its header parameter. Add a new command to print this out. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
2019-10-14imx: mmdc_size: Allow building it for i.MX7ULPFabio Estevam
i.MX7ULP uses the same MMDC controller IP as found on i.MX53 and i.MX6, so build mmdc_size.c for i.MX7ULP as well. Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-10-14imx: mmdc_size: Fix checkpatch warningsFabio Estevam
The original imx_ddr_size() implementation had some issues reported by checkpatch like this: CHECK: Prefer kernel type 'u32' over 'uint32_t' #127: FILE: arch/arm/mach-imx/mmdc_size.c:16: + uint32_t ctl; WARNING: Prefer 'unsigned int' to bare use of 'unsigned' #151: FILE: arch/arm/mach-imx/mmdc_size.c:40: + unsigned ctl = readl(&mem->ctl); Fix all of them. Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-10-14imx: Place imx_ddr_size() into a separate fileFabio Estevam
Place imx_ddr_size() into a separate file. The motivation for doing this is to be able to easily reuse imx_ddr_size() on i.MX7ULP. Currently imx_ddr_size() is inside arch/arm/mach-imx/cpu.c, which is not built for i.MX7ULP. Changing the logic to allow building cpu.c for i.MX7UP would require adding several ifdef's, leading to a not a very elegant solution. To allow better reuse, just place imx_ddr_size() into a common mmdc_size.c file. Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Stefano Babic <sbabic@denx.de>
2019-10-13ARM: dts: stm32mp1: add dsi host for stm32mp157c-dk2 boardYannick Fertré
The new class dsi host allows the management of the bridge DPI to DSI. This bridge is embedded in the chipset mp1 (come from synopsys company). Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
2019-10-13ARM: dts: stm32mp1: add dsi host for stm32mp157c-ev1 boardYannick Fertré
The new class dsi host allows the management of the bridge DPI to DSI. This bridge is embedded in the chipset mp1 (come from synopsys company). Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
2019-10-13ARM: dts: stm32f769: add display for STM32F769 disco boardYannick Fertré
Enable the display controller, mipi dsi bridge & panel. Set panel display timings. Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
2019-10-13dm: Add a dsi host uclassYannick Fertré
Display Serial Interface (DSI) host can usefully be modelled as their own uclass. DSI defines a serial bus and a communication protocol between the host and the device (panel, bridge). Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
2019-10-13imx8: Jump from alias to OCRAM address at SPL initYe Li
When running SPL on iMX8, the A core starts at address 0 which is a alias to OCRAM 0x100000. The alias only map first 96KB of OCRAM, so this require the SPL size can't beyond 96KB. But when using SPL DM, the size increase significantly and may exceed 96KB. So to fix the problem, we will change SPL linker address to OCRAM address 0x100000. And then jump to the absolute address not the PC relative address for entering OCRAM. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2019-10-13imx: tpc70: Convert TPC70 (imx6q) board to use DM/DTS in SPL and u-bootLukasz Majewski
This patch converts the TPC70 to use driver model and device tree description in both SPL and u-boot proper. Notable changes (DM/DTS conversion): - PINCTRL{_IMX6} - DM_I2C - enable 'regulator' and 'pmic' commands - DM_MMC and BLK (USDHC) - DM_ETH - DM WDT (including SYSRESET) Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-10-13imx: dts: Add u-boot specific set of device tree properties for tpc70Lukasz Majewski
This commit adds new file - imx6q-kp-u-boot.dtsi with a set of u-boot specific properties for imx6q KP device. Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-10-13imx: tpc70: dts: Add TPC70 board (imx6q based) device tree descriptionLukasz Majewski
This commit defines the TPC70 imx6q board with device tree description. Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-10-13ARM: imx6q_logic: Enable Pin muxing in SPLAdam Ford
With the 256KB of OCRAM available to SPL now, there should be enough room to enable the pinmuxing in SPL from the device tree. This patch enables SPL_PINCTRL et al and adds the serial and usdhc pin mux references to the -u-boot.dtsi file so the pins can be configured from the device tree. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-10-13ARM: dts: imx6q-tbs2910: Sync devicetree with kernel 5.3Soeren Moch
Signed-off-by: Soeren Moch <smoch@web.de>
2019-10-13Add i.MX7D based Meerkat96 board supportShawn Guo
The Meerkat96 board, based on the NXP i.MX7D SoC, is a member of 96Boards community and complies with all Consumer Edition board specifications. https://www.novtech.com/products/meerkat96.html https://www.96boards.org/product/imx7-96/ The initial supported/tested devices include: - Debug serial - SD - USB Host (with Ethernet) With these support, it's good enough for loading Linux Kernel from SD or Ethernet over USB. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2019-10-13ARM: dts: import meerkat96 board supportShawn Guo
It imports device tree source of meerkat96 board from Linux Kernel. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2019-10-12Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86Tom Rini
- Remember the device being emulated for Sandbox PCI - Update Kconfig options for FSP 1.0 - Drop RESET_BASE and RESET_SEG_SIZE that are no longer used
2019-10-12Merge branch '2019-10-11-master-imports'Tom Rini
- Assorted cleanups - FAT bugfixes - mediatek platform updates
2019-10-11arm64: print instructions leading to exceptionHeinrich Schuchardt
If an exception occurs in a loaded image and the relocation offset is unknown, it is helpful to know the instructions pointed to by the program counter. This patch adds the missing output. A possible output is: Code: 910c4021 aa1303e0 f9400662 d63f0040 (e7f7defb) The parentheses indicate the instruction causing the exception. The output can be disassembled using scripts/decodecode: echo 'Code: 90000360 9100b800 94002782 17ffff8f (e7f7defb)' | \ ARCH=arm64 scripts/decodecode Code: 90000360 9100b800 94002782 17ffff8f (e7f7defb) All code ======== 0: 90000360 adrp x0, 0x6c000 4: 9100b800 add x0, x0, #0x2e 8: 94002782 bl 0x9e10 c: 17ffff8f b 0xfffffffffffffe48 10:* e7f7defb .inst 0xe7f7defb ; undefined <-- trapping instruction Code starting with the faulting instruction =========================================== 0: e7f7defb .inst 0xe7f7defb ; undefined We already have implemented the same for armv7. For testing command 'exception undefined' can be used. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-10-11ARM: asm/io.h: remove redundant #if !defined(readb) blockRasmus Villemoes
readb is unconditionally defined earlier in io.h, so there's no point checking whether it's undefined. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2019-10-11ARM: asm/io.h: kill off confusing #ifdef __mem_pci blockRasmus Villemoes
No ARM board seems to define __mem_pci - and if it did, one would get tons of ./arch/arm/include/asm/io.h:307:0: warning: "readl" redefined warnings, because readl and friends are unconditionally defined earlier in io.h. Moreover, the redefinitions lack the memory barriers that the first definitions have. So I'm guessing this is practically dead code. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2019-10-11arm: dra7xx: Hang on any failure during IOdelay recalibrationLokesh Vutla
If there is any failure during IOdelay recalibration sequence, IOs are not guaranteed to behave as expected. So hang on any failure during the sequence. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11arm: dra7xx: Fix error path in iodelay recalibrationLokesh Vutla
When an error is reported in __recalibrate_iodelay_start(), de-isolation of IO doesn't happen. Because of this, undefined behaviour is observed on many peripherals without any error. So make sure io is out of isolation at the end of iodelay recalibration. Reported-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11arm: dts: k3-j721e-common-proc-board: Mark main_uart0 as shared deviceLokesh Vutla
Main uart0 is used as debug console by both R5SPL and A72 bootloader and Linux. So mark it as shared device so that power-domain request is successful by both cores. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11board: ti: am335x-ice: Configure the CDCE913 clock synthesizerTero Kristo
AM335x-ICE boards contain the CDCE913 clock synthesizer, and their reset crystal capacitance load value of 10pF is wrong leading into lost packets in certain networking tests. Add DT data for this device, and probe it from the board file to program the crystal capacitance load value to 0pF to avoid any problems. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-10-11board: ti: am43xx-idk: Configure the CDCE913 clock synthesizerTero Kristo
AM43xx-IDK boards contain the CDCE913 clock synthesizer, and their reset crystal capacitance load value of 10pF is wrong leading into lost packets in certain networking tests. Add DT data for this device, and probe it from the board file to program the crystal capacitance load value to 0pF to avoid any problems. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-10-11board: ti: am57xx-idk: Configure the CDCE913 clock synthesizerTero Kristo
AM57xx-IDK boards contain the CDCE913 clock synthesizer, and their reset crystal capacitance load value of 10pF is wrong leading into lost packets in certain networking tests. Add DT data for this device, and probe it from the board file to program the crystal capacitance load value to 0pF to avoid any problems. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-10-11arm: k3: Use driver_name to get ti_sci handleLokesh Vutla
Use the driver name to get ti_sci handle rather than relying on just the FIRMWARE uclass. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11arm: k3: Add support for printing CPUINFOLokesh Vutla
Add support for printing CPU info for all K3 devices. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11am335x, guardian: adapt guardian board to DMMoses Christopher
- update partition table - remove env partitions - dts: add new interfaces (uart2, extra gpio-key) remove unneeded entries update nand timings for performance improvement - defconfig: adapt configurations to suit DM remove unneeded configs - am335x_guardian.h: remove mmc boot Signed-off-by: Moses Christopher <BollavarapuMoses.Christopher@in.bosch.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-10-11am335x, guardian: update guardian boardMoses Christopher
- add BOARD_LATE_INIT function calls in board.c - add swi_status detection in board.c - mux: add guardian interfaces to single pinmux structure - am33xx, kconfig: add BOARD_LATE_INIT for GUARDIAN board Signed-off-by: Moses Christopher <BollavarapuMoses.Christopher@in.bosch.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-10-11arm: omap: emif-common: Fix memory priming for ECCKrunal Bhargav
Before the priming begins, we need to disable RMW (Read Modify Write) and disable ECC verification for read accesses. By default, the EMIF tool enables RMW and read accesses in the EMIF_ECC_CTRL_REG. Signed-off-by: Krunal Bhargav <k-bhargav@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11arm: omap: emif-common: Disable interleavingKrunal Bhargav
If ECC is enabled, we need to ensure interleaving is disabled for higher address space. Signed-off-by: Krunal Bhargav <k-bhargav@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11arm: omap: emif-common: Fix ecc address calculationLokesh Vutla
ecc_address_range registers contains the start address and end address of the DDR address space. But the ddr driver is assuming the register contains the start address and size of the DDR address space. Because of this the ecc enabling is failing for the 2nd range of ecc addresses. Fix this calculation. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11arm: dts: split mtk-reset.h into per-chip headerRyder Lee
This follows the linux header rules to avoid conflict bitfields. Tested-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2019-10-11arm: dts: add PCIe controller for MT7623 SoCRyder Lee
This adds PCIe and its PHY nodes for MT7623. Tested-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2019-10-11dt: bcm968580xref: add a spi-nor devicePhilippe Reynes
This commit add a spi-nor device in the bcm96850xref device tree. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Kursad Oney <kursad.oney@broadcom.com>
2019-10-11dt: bcm6858: add hsspi controllerPhilippe Reynes
This commit add a hsspi controller in the bcm6858 device tree. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Kursad Oney <kursad.oney@broadcom.com>
2019-10-11dt: bcm963158: add a spi-nor deviceKursad Oney
This change adds a spi nor flash device to the bcm963158 board. Signed-off-by: Kursad Oney <kursad.oney@broadcom.com> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-10-11dt: bcm63158: Add hsspi controllerKursad Oney
This change adds the hsspi controller to the 63158 dtsi. Signed-off-by: Kursad Oney <kursad.oney@broadcom.com> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-10-11armv8: K3: j721e: Updated ddr address regions in MMU tableKedar Chitnis
The A72 U-Boot code loads and boots a number of remote processors including the C71x DSP, both the C66_0 and C66_1 DSPs, and the various Main R5FSS Cores. In order to view the code loaded by the U-Boot by remote cores, U-Boot should configure the memory region with right memory attributes. Right now U-Boot carves out a memory region which is not sufficient for all the images to be loaded. So, increase this carve out region by 256MB. Signed-off-by: Kedar Chitnis <kedarc@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11armv8: K3: am65x: Update DDR address regions in MMU tableSuman Anna
The A53 U-Boot code can load and boot the MCU domain R5F cores (either a single core in LockStep mode or 2 cores in Split mode) to achieve various early system functionalities. Change the memory attributes for the DDR regions used by the remote processors so that the cores can see and execute the proper code loaded by U-Boot. These regions are currently limited to 0xa0000000 to 0xa2100000 as per the DDR carveouts assigned for these R5F cores in the overall DDR memory map. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11arm: dts: k3-am65-mcu: Add MCU domain R5F DT nodesSuman Anna
The AM65x SoCs has a single dual-core Arm Cortex-R5F processor subsystem/cluster (MCU_R5FSS0) within the MCU domain. This cluster can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. This subsystem has 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). There are some IP integration differences from standard Arm R5 clusters such as the absence of an ACP port, presence of an additional TI-specific Region Address Translater (RAT) module for translating 32-bit CPU addresses into larger system bus addresses etc. Add the DT node for the MCU domain R5F cluster/subsystem, the two R5 cores are added as child nodes to the main cluster/subsystem node. The cluster is configured to run in Split-mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11arm: dts: k3-j721e-main: Add C71x DSP nodeLokesh Vutla
The J721E SoCs have a single TMS320C71x DSP Subsystem in the MAIN voltage domain containing the next-generation C711 CPU core. The subsystem has 32 KB of L1D configurable SRAM/Cache and 512 KB of L2 configurable SRAM/Cache. This subsystem has a CMMU but is not used currently. The inter-processor communication between the main A72 cores and the C711 processor is achieved through shared memory and a Mailbox. Add the DT node for this DSP processor sub-system in the common k3-j721e-main.dtsi file. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11arm: dts: k3-j721e-main: Add C66x DSP nodesLokesh Vutla
The J721E SoCs have two TMS320C66x DSP Core Subsystems (C66x CorePacs) in the MAIN voltage domain, each with a C66x Fixed/Floating-Point DSP Core, and 32 KB of L1P & L1D configurable SRAMs/Cache and an additional 288 KB of L2 configurable SRAM/Cache. These subsystems do not have an MMU but contain a Region Address Translator (RAT) sub-module for translating 32-bit processor addresses into larger bus addresses. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. Add the DT nodes for these DSP processor sub-systems in the common k3-j721e-main.dtsi file. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11arm: dts: k3-j721e-main: Add MAIN domain R5F cluster nodesLokesh Vutla
The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS) subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within the MCU domain, and the remaining two clusters are present in the MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. These subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). There are some IP integration differences from standard Arm R5 clusters such as the absence of an ACP port, presence of an additional TI-specific Region Address Translater (RAT) module for translating 32-bit CPU addresses into larger system bus addresses etc. Add the DT nodes for these two MAIN domain R5F cluster/subsystems, the two R5 cores are each added as child nodes to the corresponding main cluster node. Configure SS0 in split mode an SS1 in lockstep mode, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11arm: dts: k3-j721e-mcu: Add MCU domain R5F cluster nodeLokesh Vutla
The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS) subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within the MCU domain, and the remaining two clusters are present in the MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. These subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). There are some IP integration differences from standard Arm R5 clusters such as the absence of an ACP port, presence of an additional TI-specific Region Address Translater (RAT) module for translating 32-bit CPU addresses into larger system bus addresses etc. Add the DT node for the MCU domain R5F cluster/subsystem, the two R5 cores are added as child nodes to the main cluster/subsystem node. The cluster is configured to run in LockStep mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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