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2014-05-22Merge branch 'pr-15052014' of git://git.denx.de/u-boot-usbTom Rini
2014-05-21arm: rmobile: koelsch: Fix QoS revision 0.240 and 0.320Nobuhiro Iwamatsu
Add register define of DBSC3 operation adjustment register, and add initial value. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-05-21arm: rmobile: r8a7791: Fix MOD_SEL3 function table about FN_SEL_IEBNobuhiro Iwamatsu
FN_SEL_IEB is assigned 2bit, and 2bit can represent 4 patterns. However FN_SEL_IEB but we only use 3. It adds empty patterns as 0. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-05-21gpio: r8a7790-gpio: Fix typo in macroNobuhiro Iwamatsu
Fix typo from __ASM_R8A7790_H__ to __ASM_R8A7790_GPIO_H__. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-05-21gpio: r8a7791-gpio: Fix typo in macroNobuhiro Iwamatsu
Fix typo from __ASM_R8A7791_H__ to __ASM_R8A7791_GPIO_H__. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-05-21arm: rmobile: Add define of SCIF register for R8A7790 and R8A7791Nobuhiro Iwamatsu
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-05-20Merge remote-tracking branch 'u-boot/master'Albert ARIBAUD
Conflicts: boards.cfg Conflicts were trivial once u-boot-arm/master boards.cfg was reformatted (commit 6130c146) to match u-boot/master's own reformatting (commit 1b37fa83).
2014-05-16Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini
2014-05-16mpc85xx/p1020:Define number of USB controllers used on P1020RDB-PD platformramneek mehresh
P1020 SoC which has two USB controllers, but only first one is used on this platform. Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-16powerpc/mpc85xx: Added B4460 supportShaveta Leekha
B4460 differs from B4860 only in number of CPU cores, hence used existing support for B4860. B4460 has 2 PPC cores whereas B4860 has 4 PPC cores. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-16fsl/pci: Add workaround for erratum A-005434Chunhe Lan
By default, all PEX inbound windows PEX_PEXIWARn[TRGT] are mapped to 0xF, which is local memory. But for BSC9132, 0xF is CCSR, 0x0 is local memory. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-16Merge remote-tracking branch 'u-boot-sh/rmobile'Albert ARIBAUD
Conflicts: boards.cfg Trivial conflict, maintainer change plus board addition
2014-05-16Revert "sandbox: move source files from board/ to arch/sandbox/"Masahiro Yamada
This reverts commit 258060905e04fe2eb509756ef3b37e23e220a2d6. Conflicts: boards.cfg Wrong patch 25806090 was applied by accident. Revert it. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2014-05-16Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD
2014-05-16Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD
2014-05-16ARM: dts: exnyos: enable dw-mmc controllerJaehoon Chung
Enabled the dw-mmc controller. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-16ARM: dts: exynos: rename from EXYNOS5_DWMMC to EXYNOS_DWMMCJaehoon Chung
Exynos serise can be supported the dw-mmc controller. So, it's good that used the general prefix as "_EXYNOS_DWMMC". Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-16ARM: exynos: clock: modify the set_mmc_clk for exynos4Jaehoon Chung
Modified the mmc_set_clock for eynos4. The goal of this patch is that fsys-div register should be reset. And retore the div-value, not using the value of lowlevel_init. (For using SDMMC4, this patch is needs) Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-16board: trats2: Enable device tree on Trats2Beomho Seo
This patch add dwmmc emmc controller node on exynos4 and exynos4412 device tree. Signed-off-by: Beomho Seo <beomho.seo@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Piotr Wilczek <p.wilczek@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Piotr Wilczek <p.wilczek@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-16arm: exynos: clock: Remove exynos4x12_set_mmc_clk functionBeomho Seo
exynos4x12_set_mmc_clk function have been removed. Because, exynos4x12_clock and exynos4_clock return same div_fsys* value. Signed-off-by: Beomho Seo <beomho.seo@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Piotr Wilczek <p.wilczek@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Piotr Wilczek <p.wilczek@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-16arm: exynos: pinmux: add sdmmc4 gpio configratuionBeomho Seo
For use dwmmc controller at exynos4, add SDMMC4 gpio configuration. Signed-off-by: Beomho Seo <beomho.seo@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Piotr Wilczek <p.wilczek@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Piotr Wilczek <p.wilczek@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-15Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master'Albert ARIBAUD
2014-05-15Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD
2014-05-15arm: move exception handling out of start.S filesAlbert ARIBAUD
Exception handling is basically identical for all ARM targets. Factorize it out of the various start.S files and into a single vectors.S file, and adjust linker scripts accordingly. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2014-05-15arm: remove unused _end_vect and _vectors_end symbolsAlbert ARIBAUD
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2014-05-15arm: pxa: move SP check from start.S to cpuinfo.cAlbert ARIBAUD
PXA start.S has a PXA (variant) specific check in start.S. Move it to cpuinfo.c. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Marek Vasut <marex@denx.de>
2014-05-15arm: move reset_cpu from start.S into cpu.cAlbert ARIBAUD
CPUs arm946es and sa1100 both define the reset_cpu() function in their start.S file. Move this cpu-specific code into cpu.c so that start.S only contains ARM generic code. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2014-05-15arm1136: move cache code from start.S to cache.cAlbert ARIBAUD
arch/arm/cpu/arm1136/start.S contain a cache flushing function. Remove the function and move its code into arch/arm/lib/cache.c. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2014-05-15zynq: add UART nodes to device tree to initialize UART with OFMasahiro Yamada
Commit c9416b92 added OF UART initialization support but aliases nodes are missing in device tree. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Michal Simek <michal.simek@xilinx.com> Tested-by: Masahiro Yamada <yamada.m@jp.panasonic.com> [on ZC706 board] Tested-by: Michal Simek <michal.simek@xilinx.com> [on ZC702 board] Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-15zynq: add memory nodes to device tree to initialize DRAM with OFMasahiro Yamada
Commit 9e0e37ac added OF RAM initialization support but memory nodes are missing in device tree. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Michal Simek <michal.simek@xilinx.com> Tested-by: Masahiro Yamada <yamada.m@jp.panasonic.com> [on ZC706 board] Tested-by: Michal Simek <michal.simek@xilinx.com> [on ZC702 board] Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-15zynq: import zynq-7000.dtsi from Linux KernelMasahiro Yamada
Our current motivation is to use OF initialization for RAM and UART. But adding full DTS would be helpful in future, for instance, for OF configuration of Ethernet, MMC, USB, etc. This commit imports arch/arm/boot/dts/zynq-7000.dtsi from Linux 3.15-rc5 and adjusts the license comment block for SPDX. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Suggested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-15Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic
2014-05-15usb: tegra: support device modeStephen Warren
A few changes are made to the Tegra EHCI driver so that it can set everything up for device-mode operation on the first USB controller. This can be used in conjunction with ci_udc.c to operate as a USB device. Detailed changes are: * Rename set_host_mode() to set_up_vbus() since that's really what it does. * Modify set_up_vbus() to know whether it's initializing in host or device mode, and: - Skip the external VBUS check in device mode, since external VBUS is expected in this case. - Disable VBUS output in device mode. * Modify init_phy_mux() to know whether it's initializing in host or device mode, and hence skip setting USBMODE_CM_HC (which enables host mode) in device mode. See the comments in that function for why this is safe w.r.t. the ordering requirements of PHY selection. * Modify init_utmi_usb_controller() to force "b session valid" in device mode, since the HW requires this. This is done in UTMI-specific code, since we only support device mode on the first USB controller, and that controller can only talk to a UTMI PHY. * Enhance ehci_hcd_init() to error-check the requested host-/device-mode vs. the dr_mode (dual-role mode) value present in device tree, and the HW configurations which support device mode. * Enhance ehci_hcd_init() not to skip HW initialization when switching between host and device mode on a controller. This requires remembering which mode the last initialization used. Cc: Jim Lin <jilin@nvidia.com> Cc: Stefan Agner <stefan@agner.ch> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-05-14zynq: treat ps7_init.c/h as external files to ignore themMasahiro Yamada
ps7_init.c and ps7_init.h are supposed to be exported by hw project and copied to board/xilinx/zynq/ directory. We want them to be ignored by git. So what we should do is to always treat them as external files rather than replacing ps7_init.c This commit does: - Move a weak function ps7_init() to arch/arm/cpu/armv7/zynq/spl.c and delete board/xilinx/zynq/ps7_init.c - Compile board/xilinx/zynq/ps7_init.c only when it exists - Add .gitignore to ignore ps7_init.c/h Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-14ARM: zynq: ehci: Added USB host driver supportMichal Simek
Added USB host driver for zynq. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-14ARM: zynq: Add MIO detection codeMichal Simek
Add run-time MIO pin detection to get actual pin configuration for specific periphery. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-14ARM: zynq: Fix bootmode maskMike Looijmans
Bootmode mask was defined as 0x0F, but documentation mentions 0x07. Experiments show that bit "3" is the JTAG chain configuration. Change the mask to "7" to allow systems with a different chain configuration to boot correctly. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-14ARM: zynq: Setup correct slcr_lock valueMichal Simek
The driver should setup slcr state according to slcr operations. Reported-by: Andrey Filippov <andrey@elphel.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-14ARM: zynq: slcr: Fix incorrect commentaryMichal Simek
Fix c&p error in zynq_slcr_devcfg_enable() commentary and extending it with description according to Zynq TRM also in zynq_slcr_devcfg_disable(). Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-14ARM: zynq: Call zynq board_init() in SPLMichal Simek
Call board_init() if SPL is configured with CONFIG_SPL_BOARD_INIT. Signed-off-by: Michal Simek <monstr@monstr.eu>
2014-05-14ARM: zynq: Do not use half memory size for ECC caseMichal Simek
Memory size should be specified without ECC place. If you need to have half memory size, please change u-boot configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-14ARM: zynq: Added efuse status register base addressSiva Durga Prasad Paladugu
Added efuse status register base address. This register is used for determining whether efuse was blown or not. Also, added the zynq_get_silicon_version() to get the silicon version of the zynq board. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-14ARM: zynq: Fix sparse warning in ddrc.cMichal Simek
Warning: arch/arm/cpu/armv7/zynq/ddrc.c:43:24: warning: Using plain integer as NULL pointer Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-14ARM: zynq: Fix sparse warnings in slcr.cMichal Simek
Warnings: arch/arm/cpu/armv7/zynq/slcr.c:21:6: warning: symbol 'zynq_slcr_lock' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:27:6: warning: symbol 'zynq_slcr_unlock' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:34:6: warning: symbol 'zynq_slcr_cpu_reset' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:54:6: warning: symbol 'zynq_slcr_gem_clk_setup' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:81:6: warning: symbol 'zynq_slcr_devcfg_disable' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:94:6: warning: symbol 'zynq_slcr_devcfg_enable' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:107:5: warning: symbol 'zynq_slcr_get_boot_mode' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:113:5: warning: symbol 'zynq_slcr_get_idcode' was not declared. Should it be static? Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-13ARM: OMAP5: add CKO buffer control maskDmitry Lifshitz
Add CKOBUFFER_CLK_EN bit mask enabling FREF_XTAL_CLK clock. Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
2014-05-13ARM: OMAP5: add UART4 supportDmitry Lifshitz
Add UART4 base address. Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
2014-05-13am33xx: add SSC enable macroYegor Yefremov
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
2014-05-13ARM: tegra: use a CPU freq that all SKUs can supportStephen Warren
U-Boot on Tegra30 currently selects a main CPU frequency that cannot be supported at all on some SKUs, and needs higher VDD_CPU/VDD_CORE values on some others. This can result in unreliable operation of the main CPUs. Resolve this by switching to a CPU frequency that can be supported by any SKU. According to the following link, the maximum supported CPU frequency of the slowest Tegra30 SKU is 600MHz: repo http://nv-tegra.nvidia.com/gitweb/?p=linux-2.6.git;a=summary branch l4t/l4t-r16-r2 path arch/arm/mach-tegra/tegra3_dvfs.c table cpu_dvfs_table[] According to that same table, the minimum VDD_CPU required to operate at that frequency across all SKUs is 1.007V. Given the adjustment resolution of the TPS65911 PMIC that's used on all Tegra30-based boards we support, we'll end up using 1.0125V instead. At that VDD_CPU, tegra3_get_core_floor_mv() in that same file dictates that VDD_CORE must be at least 1.2V on all SKUs. According to tegra_core_speedo_mv() (in tegra3_speedo.c in the same source tree), that voltage is safe for all SKUs. An alternative would be to port much of the code from tegra3_dvfs.c and tegra3_speedo.c in the kernel tree mentioned above. That's more work than I want to take on right now. While all the currently supported boards use the same regulator chip for VDD_CPU, different types of regulators are used for VDD_CORE. Hence, we add some small conditional code to select how VDD_CORE is programmed. If this becomes more complex in the future as new boards are added, or we end up adding code to detect the SoC SKU and dynamically determine the allowed frequency and required voltages, we should probably make this a runtime call into a function provided by the board file and/or relevant PMIC driver. Cc: Alban Bedel <alban.bedel@avionic-design.de> Cc: Marcel Ziswiler <marcel@ziswiler.com> Cc: Bard Liao <bardliao@realtek.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-05-13ARM: tegra: add function to enable input clamping on tristateStephen Warren
The HW-defined procedure for booting Tegra requires that CLAMP_INPUTS_WHEN_TRISTATED be enabled before programming the pinmux. Add a function to the pinmux driver to allow boards to do this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-05-13ARM: tegra: add GPIO initialization table functionStephen Warren
The HW-defined procedure for booting Tegra requires that some pins be set up as GPIOs immediately at boot in order to avoid glitches on those pins, when the pinmux is programmed. Add a feature to the GPIO driver which executes a GPIO configuration table. Board files will use this to implement the correct HW initialization procedure. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
generated by cgit (git 2.34.1) at 2024-12-28 10:51:41 +0000