summaryrefslogtreecommitdiff
path: root/arch
AgeCommit message (Collapse)Author
2019-02-28ARM: cache: Fix incorrect bitwise operationMarek Vasut
The loop implemented in the code is supposed to check whether the PL310 operation register has any bit from the mask set. Currently, the code checks whether the PL310 operation register has any bit set AND whether the mask is non-zero, which is incorrect. Fix the conditional. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Tom Rini <trini@konsulko.com> Fixes: 93bc21930a1b ("armv7: add PL310 support to u-boot") Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2019-02-27riscv: Enable CONFIG_SYS_BOOT_RAMDISK_HIGH for using initrdAnup Patel
This patch enables CONFIG_SYS_BOOT_RAMDISK_HIGH for RISC-V because bootm will update initrd location in DTB only if CONFIG_SYS_BOOT_RAMDISK_HIGH is enabled. If we don't enable this option then bootm assumes DTB already has initrd details which is not the case most of the time. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-02-27riscv: Add SiFive FU540 board supportAnup Patel
This patch adds SiFive FU540 board support. For now, only SiFive serial, SiFive PRCI, and Cadance MACB drivers are only enabled. The SiFive FU540 defconfig by default builds U-Boot for S-Mode because U-Boot on SiFive FU540 will run in S-Mode as payload of BBL or OpenSBI. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-27clk: Add fixed-factor clock driverAnup Patel
This patch adds fixed-factor clock driver which derives clock rate by dividing (div) and multiplying (mult) fixed factors to a parent clock. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-27riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systemsAnup Patel
On 64bit systems, the DRAM top can be easily beyond 4GB and U-Boot DMA mapping APIs will generate DMA addresses beyond 4GB. This breaks DMA programming in 32bit DMA capable devices (such as Cadence MACB ethernet). For example, If DRAM is more then 2GB on QEMU sifive_u machine then Cadence MACB ethernet stops working for U-Boot because it is a 32bit DMA capable device. To handle 32bit DMA capable devices on 64bit systems, we provide custom implementation of board_get_usable_ram_top() which ensures that usable ram top is not more then 4GB. This in-turn ensures that U-Boot always runs within 4GB hence DMA addresses generated by DMA mapping APIs will be within 4GB too. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-27riscv: Add place-holder asm/arch/clk.h for driver compilationAnup Patel
Some of the drivers (such as Cadence MACB ethernet driver) expect asm/arch/clk.h to be provided by arch support so we add place-holder asm/arch-generic/clk.h for RISC-V generic CPU. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-02-27riscv: Add asm/dma-mapping.h for DMA mappingsAnup Patel
This patch adds asm/dma-mapping.h for Linux-like DMA mappings APIs required by some of the drivers (such as, Cadance MACB Ethernet driver). Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-02-27riscv: Rename cpu/qemu to cpu/genericAnup Patel
The QEMU CPU support under arch/riscv is pretty much generic and works fine for SiFive Unleashed as well. In fact, there will be quite a few RISC-V SOCs for which QEMU CPU support will work fine. This patch renames cpu/qemu to cpu/generic to indicate the above fact. If there are SOC specific errata workarounds required in cpu/generic then those can be done at runtime in cpu/generic based on CPU vendor specific DT compatible string. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-27riscv: Enable create symlink using kconfigAnup Patel
We select CREATE_ARCH_SYMLINK for RISC-V so that we can have include/asm/arch linked to include/asm/arch-xyz. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini
2019-02-20Merge git://git.denx.de/u-boot-x86Tom Rini
- Add support for sound. Albeit the big changeset, changes are pretty limited to x86 only and a few new sound drivers used by x86 so I think it would be good to have this in the next release.
2019-02-20Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
- Support of NXP's LX2160RDB and LX2160QDS platform - Enable SATA DM model for NXP's ARM SoCs
2019-02-20ARM: tegra: enable ums on nyan boardsTristan Bastian
This patch enables UMS on the nyan devices like the nyan-big. A patch like this has been sent in by Stephen Warren some time ago for other tegra devices: commit e6607cffef965011ef0ddc0fbe6f4b7c0d53aeec. But the nyan devices never received that functionality. Signed-off-by: Tristan Bastian <tristan-c.bastian@gmx.de> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-02-20nyan-big: change spi delayTristan Bastian
Internal keyboard of nyan-big is only working when cold booting by pressing [reload/refresh]+[power] button. With this patch keyboard is working by only pressing [power] button. Signed-off-by: Tristan Bastian <tristan-c.bastian@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-02-20x86: Add sound support for samusSimon Glass
Enable sound on samus using the broadwell I2S and an RT5677 audio codec. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2019-02-20x86: broadwell: Add support for serial I/O devicesSimon Glass
Add support for initing the I2C device and ADSP on broadwell. These are needed for sound to work. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20x86: broadwell: Don't bother probing the PCH for pinctrlSimon Glass
At present the pinctrl probes the PCH but since it only uses it to obtain a PCI address, this is no necessary. Avoiding this fixes one of the two co-dependent loops in broadwell. This driver really should be a proper pinctrl driver, but for now it remains a syscon device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20x86: broadwell: Add support for the ADSPSimon Glass
The Application Digital Signal Processor is used for sound processing with broadwell. Add a driver to support this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20sound: x86: Add beeping support in i8254Simon Glass
Adjust the code to allow beeping at different frequencies, using a calculated value for timer 2. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20sound: x86: link: Add sound supportSimon Glass
Add sound support for link, using the HDA codec implementation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20sandbox: sound: Silence sound for testingSimon Glass
When testing the sound system we don't need the hear the beeps. The testing works by checking the data that would be emitted. Add a device-tree property to silence the sound, and enable it for testing. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20sound: Add uclass operations for beepingSimon Glass
Some audio codecs such as Intel HDA do not need to use digital data to play sounds, but instead have a way to emit beeps. Add this interface as an option. If the beep interface is not supported, then the sound uclass falls back to the I2S interface. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20x86: ivybridge: Add a way to get the HDA config settingSimon Glass
Add a way check to whether HD audio is enabled. Use ioctl() to avoid adding too many unusual operations to PCH. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20sandbox: pch: Add a test for the PCH uclassSimon Glass
This uclass currently has no tests. Add a sandbox driver and some simple tests to provide basic coverage. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: Use "sandbox,pch" for the compatible string, for consistency] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20x86: sandbox: pch: Add a CONFIG option for PCHSimon Glass
At present this uclass is selected only on x86. In order to add a test for it, it must also support sandbox. Create a new CONFIG_PCH option and enable it on x86 and sandbox. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20x86: Adjust I/O macros to work on 64-bit machinesSimon Glass
At present these macros give warnings on 64-bit machines and do not correctly do 32-bit accesses. Update them to use linux types. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20sandbox: Add a note about the growing state_info structSimon Glass
This struct is getting larger and in some cases is being used for things which would be better put into a driver. For example hwspinlock is not used outside of sandbox_hwspinlock.c. Add a note to encourage people to put things elsewhere. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-19ARM: omap3: evm: Update DM SPL supportDerald D. Woods
- Switch to using the omap3-u-boot.dtsi file for needed properties - Enable SPL_OF_CONTROL This commit is based on the following series: https://patchwork.ozlabs.org/project/uboot/list/?series=92472 https://patchwork.ozlabs.org/project/uboot/list/?series=92462 Signed-off-by: Derald D. Woods <woods.technical@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-02-19omap3_beagle: Update for DM SPL supportTom Rini
- Switch to using the omap3-u-boot.dtsi file for needed properties. - Remove a few SPL features to free up more SRAM space. - Switch CONFIG_SYS_TEXT_BASE to the normal default, we don't need to worry about X-Loader at this point anymore. - A few related updates to SPL options as part of switching to DM SPL. Signed-off-by: Tom Rini <trini@konsulko.com> Tested-by: Derald D. Woods <woods.technical@gmail.com>
2019-02-19ARM: omap3_logic: Enable SPL booting device treeAdam Ford
With the generic omap3-u-boot.dtsi file available, this patch increased the memory of the various incarnations of the omap3_logic board, and points their respective u-boot.dtsi files to the newly created generic one, and removes the PLATDATA from the board file. These are all done at once because the're all utilizing the same omap3logic.c board file. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-02-19ARM: DTS: omap3-u-boot.dtsiAdam Ford
Create generic omap3-u-boot.dtsi file that omap3 based boards can include to generate device tree in SPL for booting MLO. Credit should go to Tom Rini. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> Tested-by: Derald D. Woods <woods.technical@gmail.com>
2019-02-19board/BuR/brxre1: convert do DMHannes Schmelzer
This commit converts the brxre1 board to DM, for this we have todo following things: - add a devicetree-file for this board - drop all obsolete settings from board header-file - use dm_i2c_xxx calls for read/write to the resetcontroller - request gpios before operate them Serues-cc: trini@konsulko.com Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
2019-02-19armv8: ls1043a: move SCSI_AHCI and SCSI to arm/KconfigPeng Ma
remove SCSI and SCSI_AHCI configs for ls1043ardb due to no sata interface support. this changed is to fixed the ls1043ardb compile warning as fallows: ===================== WARNING ====================== This board does not use CONFIG_DM_SCSI. Please update the storage controller to use CONFIG_DM_SCSI before the v2019.07 release. Failure to update by the deadline may result in board removal.See doc/driver-model/MIGRATION.txt for more info. ==================================================== Signed-off-by: Peng Ma <peng.ma@nxp.com> [PK: reword the patch subject] Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19armv8: layerscape: move CONFIG_LAYERSCAPE to KconfigRajesh Bhagat
Moves CONFIG_LAYERSCAPE for all NXP Layerscape platforms. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19armv8: layerscape: move TZASC and TZPC configs to KconfigRajesh Bhagat
Moves FSL_TZASC_400 and FSL_TZPC_BP147 configs to Kconfig for LS1088A and LS2088A platforms. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19lx2160aqds : Add support for LX2160AQDS platformPankaj Bansal
LX2160AQDS is a development board that supports LX2160A family SoCs. This patch add base support for this board. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> [PK: Sqaush patch for "secure boot defconfig" & add maintainer] Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19armv8: emc2305: add support for fan controllerMeenakshi Aggarwal
Add support for fan controller emc2305. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19armv8: lx2160ardb : Add support for LX2160ARDB platformPriyanka Jain
LX2160ARDB is an evaluation board that supports LX2160A family SoCs. This patch add base support for this board. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Peng Ma <peng.ma@nxp.com> Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> [PK: Sqaush patches from Yinbo Zhu, Peng Ma, Chuanhua Han and re-arrange defconfig] Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19armv8: fsl-layerscape: reorder rgmii dpmacs' enablementPankaj Bansal
some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19armv8, lx2160a: Initialize ethernet array in serdes_initPriyanka Jain
Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19arch: arm: lib: Flush L3 after relocation to DDRMeenakshi Aggarwal
Flush L3 cache after uboot relocated to DDR. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Udit Kumar <udit.kumar@nxp.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19armv8: lx2160a: Update CONFIG_SYS_FSL_PEBUF_BASEPriyanka Jain
As per hardware documentation, CONFIG_SYS_FSL_PEBUF_BASE for lx2160a is 0x1c00000000 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-18arm: socfpga: gen5: remove hacked ETH RST handlingSimon Goldschmidt
The 'dwmac_socfpga' ETH driver can now get the MACs out of reset via the socfpga reset driver and can set PHY mode via syscon. This means we can now remove the ad-hoc code to do this from arch/arm/mach-socfpga. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-02-16Merge tag 'u-boot-imx-2019-02-16' of git://git.denx.de/u-boot-imxTom Rini
u-boot-imx-2019-02-16 --------------------- - vhybrid: add calibration - gw_ventana: fixes - Improve documentation for Secure Boot (HABv4) - Fix Marvell Switch - MX6 Sabre, switch to DM - Fixes for NAND
2019-02-15imx: cpu.c: give access to reset cause in splMax Krummenacher
This makes get_imx_reset_cause() accessible in SPL, but keeps the SRSR register content intact so that U-Boot proper can evaluated the reset_cause again should this be needed. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2019-02-15ARM: dts: i.MX6Q, i.MX6QDL: fix address/size-cells warningsMarcel Ziswiler
This fixes the following warnings: arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size): /clocks: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size): /soc/aips-bus@02100000/mipi@021e0000: unnecessary #address-cells/ #size-cells without "ranges" or child "reg" property arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size): /soc/ipu@02400000/port@2: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size): /soc/ipu@02400000/port@3: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size): /soc/ipu@02800000/port@2: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size): /soc/ipu@02800000/port@3: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2019-02-15arm: dts: Update all the dts[i] files for imx6[q|qp|dl] sabre[auto|sd]Abel Vesa
Update all the dts[i] files for imx6[q|qp|dl] sabre[auto|sd] to the ones from kernel v4.20 (commit 8fe28cb58bcb2). Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-02-15arm: dts: Add all the imx6[q|qp|dl] sabre[auto|sd] u-boot dts[i] filesAbel Vesa
This allows us to keep the basic dts[i] files up-to-date with the ones in kernel, but at the same time allowing the u-boot to add its own properties to the existing nodes. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-02-15usb: Rename SPL_USB_SUPPORT to SPL_USB_STORAGEAbel Vesa
Since there is the SPL_USB_HOST_SUPPORT for enabling USB support in SPL, makes more sense to rename the SPL_USB_SUPPORT as SPL_USB_STORAGE. Everything that is not part of the usb storage support in SPL is now build under SPL_USB_HOST_SUPPORT. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-02-15arm64: zynqmp: Change the spi-rx-bus-width property to x1Venkatesh Yadav Abbarapu
As per the zc1275 design x1 mode is enabled so changing the spi-rx-bus-width property to x1. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
generated by cgit (git 2.34.1) at 2025-01-07 21:09:05 +0000