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2019-05-08Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini
- Various PHY fixes / enhancements. - TI K2G fixes
2019-05-08net: phy: micrel: Use correct skew values on KSZ9021James Byrne
Commit ff7bd212cb8a ("net: phy: micrel: fix divisor value for KSZ9031 phy skew") fixed the skew value divisor for the KSZ9031, but left the code using the same divisor for the KSZ9021, which is incorrect. The preceding commit c16e69f702b1 ("net: phy: micrel: add documentation for Micrel KSZ90x1 binding") added the DTS documentation for the KSZ90x1, changing it from the equivalent file in the Linux kernel to correctly state that for this part the skew value is set in 120ps steps, whereas the Linux documentation and driver continue to this day to use the incorrect value of 200 that came from the original KSZ9021 datasheet before it was corrected in revision 1.2 (Feb 2014). This commit sorts out the resulting confusion in a consistent way by making the following changes: - Update the documentation to be clear about what the skew values mean, in the same was as for the KSZ9031. - Update the Micrel PHY driver to select the appropriate divisor for both parts. - Adjust all the device trees that state skew values for KSZ9021 PHYs to use values based on 120ps steps instead of 200ps steps. This will result in the same values being programmed into the skew registers as the equivalent device trees in the Linux kernel do, where it incorrectly uses 200ps steps (since that's where all these device trees were copied from). Signed-off-by: James Byrne <james.byrne@origamienergy.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-05-08Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini
- H6 Beelink GS1 board (Clément) - Olimex A64-Teres-I board (Jonas) - sunxi build fix for CONFIG_CMD_PXE|DHCP (Ondrej) - Change include order (Jagan) - EPHY clock changes (Jagan) - EMAC enablement on Cubietruck Plus, BPI-M3 (Chen-Yu Tsai)
2019-05-09sun50i: a64: Add Olimex A64-Teres-I board initial supportJonas Smedegaard
Olimex A64-Teres-I board is a mainboard (the only one so far) for Olimex Teres-I DIY laptop kit. Key features: - Allwinner A64 Cortex-A53 - Mali-400MP2 GPU - AXP803 PMIC - 2GB DDR3 RAM - MicroSD Slot - 16GB eMMC Flash - eDP LCD display - HDMI - USB Host - Battery management - 5V DC power supply - Certified Open Source Hardware (OSHW) Works: - i2C - MMC/SD - PWM backlight Known broken: - Internal keyboard (seems to be because the keyboard firmware loads a bootloader first, and then disconnects bootloader and connect real keyboard). External ones connected to the USB port work fine. This patch enables support for the A64-Teres-I board to u-boot, including enabling screen backlight (lacking from Linux device-tree). Linux commit details about the sun50i-a64-teres-i.dts sync: "arm64: dts: allwinner: a64: Rename uart0_pins_a label to uart0_pb_pins" (sha1: d91ebb95b96c8840932dc3a10c9f243712555467) Cosmetic warnings regarding whitespace and placement of SPDX notice for dts file was ignored. config and .dtsi file are adapted from pinebook files. Tested-by: Jonas Smedegaard <dr@jones.dk> Signed-off-by: Jonas Smedegaard <dr@jones.dk> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> [jagan: move board entry in MAINTAINERS file at proper position] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-05-08rockchip: dts: rk3399: Sync rk3399-nanopi4.dtsi from LinuxJagan Teki
Sync rk3399-nanopi4.dtsi from Linux 5.1-rc2 tag. Linux commit details about the rk3399-nanopi4.dtsi sync: "arm64: dts: rockchip: Add nanopi4 bluetooth" (sha1: 3e2f0bb72be36aa6c14ee7f11ac4dd8014801030) Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08arm: rockchip: rk3399: Move common configs in KconfigJagan Teki
Few SPL and U-Boot proper configs are common to all rk3399 target defconfigs, move them and select it from platform kconfig. Moved configs: - SPL_ATF - SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF - SPL_LOAD_FIT - SPL_CLK if SPL - SPL_PINCTRL if SPL - SPL_RAM if SPL - SPL_REGMAP if SPL - SPL_SYSCON if SPL - CLK - FIT - PINCTRL - RAM - REGMAP - SYSCON - DM_PMIC - DM_REGULATOR_FIXED Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: dts: rk3399: Sync pwm2_pin_pull_down from Linux 5.1-rc2Jagan Teki
To make successful build with dts(i) files syncing from Linux 5.1-rc2 the rk3399.dtsi would require pwm2_pin_pull_down. So, sync the pwm2_pin_pull_down node from Linux 5.1-rc2. Since this node is strictly not part of any commit alone, I have mentioned Linux 5.1-rc2 tag for future reference of where would this sync coming from. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08arm64: rockchip: dts: rk3399: Use rk3399-u-boot.dtsiJagan Teki
Now we have - board specific -u-boot.dtsi files for board specific u-boot dts changes. - soc specific rk3399-u-boot.dtsi for soc specific u-boot dts changes. So, include the rk3399-u-boot-dtsi on respective board -u-boot.dtsi and drop the properties which are globally available in rk3399-u-boot.dtsi Right now rk3399-u-boot.dtsi has sdmmc, spi1 u-boot,dm-pre-reloc property and more properties and nodes can be move further based on the requirements. This would fix, the -u-boot.dtsi inclusion for evb, firefly, puma boards that was accidentally merged on below commit. "rockchip: dts: rk3399: Create initial rk3399-u-boot.dtsi" (sha1: e05b4a4fa84b65a0c8873e8f34721741fe2bc09d) Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: dts: rk3399-u-boot: Add u-boot, dm-pre-reloc for spi1Jagan Teki
Add u-boot,dm-pre-reloc property for spi1, so-that the subsequent rk3399 boards which boot from SPI. This help to separate the u-boot specific properties away from base dts files so-that the Linux sync become easy and meaningful. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08arm64: rockchip: dts: rk3399: Add board -u-boot.dtsi filesJagan Teki
Devicetree files in RK3399 platform is synced from Linux, like other platforms does. Apart from these u-boot in rk3399 would also require some u-boot specific node like dmc. dmc node has big chunk of DDR timing parameters which are specific to specific board, and maintained with rk3399-sdram*.dtsi. So, create board specific -u-boot.dtsi files and move these sdram dtsi files accordingly. This would help of maintain u-boot specific changes separately without touching Linux dts(i) files which indeed easy for syncing from Linux between releases. These board specific -u-boot.dtsi can be extendible to add more u-boot specific nodes or properties in future. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08dts: Makefile: Build rockchip dtbs based on SoC typesJagan Teki
- Sometimes u-boot specific dtsi files are included automatically which would build for entire rockchip SoC, even-though the respective dtsi should used it for specific family of rockchip SoC. - Sometimes u-boot specific dts nodes or properties can use config macros from respective rockchip family include/configs files, example CONFIG_SPL_PAD_TO. So, it's better to compile the dtbs based on the respective rockchip family types rather than rockchip itself to avoid compilation issues. This patch organize the existing dtb's based on the rockchip family types. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: chromebook_minnie: Enable soundSimon Glass
Enable sound for this board, which has the same codec as jerry. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: rk3399: add tpl supportKever Yang
Rockchip platform suppose to use TPL(run in SRAM) as dram init and SPL(run in DDR SDRAM) as pre-loader, so that the SPL would not be limited by SRAM size. This patch add rk3399-board-tpl.c and its common configs. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: add u-boot-tpl-v8.ldsKever Yang
We don't have both sram and sdram in TPL, so update from: arch/arm/cpu/armv8/u-boot-spl.lds Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-05-08rockchip: px5: add timer0 dts node as tick timerKever Yang
Let's use rockchip timer before stimer patches can be merged. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: rk3368: remove uart iomux init in SPLKever Yang
The iomux should have been set in board_debug_uart_init(), do not set in board_init_f(), remove it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: boot0: update CONFIG_ROCKCHIP_SPL_RESERVE_IRAM for SPL onlyKever Yang
The CONFIG_ROCKCHIP_SPL_RESERVE_IRAM is for SPL only, add condition to limit it not affect TPL. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: px5 update dts for spl/tplKever Yang
TPL need dmc to init ddr sdram, and emmc, boot-order. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Andy Yan <andy.yan@rock-chips.com>
2019-05-08rockchip: rk3368: support UART2/4 in board_debug_uart_init()Kever Yang
evb-rk3368 is using UART2 and PX5 evb is using UART4 Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Andy Yan <andy.yan@rock-chips.com>
2019-05-08rockchip: rk322x: dts: enable uart2 for SPL/TPLKever Yang
When we use DM_SERIAL for serial driver, we need enable the dts node for the debug console. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08sysreset: enable driver support in SPL/TPLKever Yang
SPL/TPL also need use sysreset for some feature like panic callback. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: rk322x: add tpl supportKever Yang
Move original spl to tpl, and add spl to load next stage firmware, adapt all the address and option for them. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08arm: add a separate stack for TPLKever Yang
TPL stack may different from SPL and sys stack, add support for separate one when the board defines it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08arm: add option for TPL support in arm 32bitKever Yang
Some options like TPL_SYS_THUMB_BUILD, TPL_USE_ARCH_MEMCPY and TPL_USE_ARCH_MEMCPY are needed for TPL build in 32bit arm. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08arm: remove ARCH_ROCKCHIP macro in common codeKever Yang
This is fix to: e2a12f590d rockchip: use 'arch-rockchip' as header file path The V2 of origin patch set has fix this, but we merge V1 by mistake, so lets correct it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: add common header boot0.h and gpio.h for socKever Yang
boot0.h and gpio.h will be used by system and include by 'asm/arch/', each of them need of a copy from 'asm/arch-rockchip'. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-05-08x86: samus: Update device tree for verified bootSimon Glass
Add nvdata drivers for the TPM and RTC as used on samus. These are needed for Chromium OS verified boot on samus. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: samus: Update device tree for SPLSimon Glass
Add tags to allow required nodes to be present in SPL / TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Add a simple TPL implementationSimon Glass
Add the required CPU code so that TPL builds correctly. Also update the SPL code to deal with being booted from TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Add a way to jump from TPL to SPLSimon Glass
When TPL finishes it needs to jump to SPL with the stack set up correctly. Add a function to handle this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: broadwell: Update PCH to work in TPLSimon Glass
The early init should only happen once. Update the probe method to deal with TPL, SPL and U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Enable the RTC on all boardsSimon Glass
With the move to Kconfig this option should be set in Kconfig, not in the config header file. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Fix device-tree indentationSimon Glass
With the use of a phandle we can outdent the device tree nodes a little. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Update device tree for Chromium OS verified bootSimon Glass
The standard image generated by U-Boot on x86 is u-boot.rom. Add a separate image called image.bin for verified boot. This supports verification in TPL of which SPL/U-Boot to start, then jumping to the correct one, with SPL setting up the SDRAM and U-Boot proper providing the user interface if needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Update device tree for TPLSimon Glass
Add TPL binaries to the device x86 binman desciption. When enabled, TPL will start first, doing the 16-bit init, then jump to SPL and finally U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Don't generate a bootstage report in SPLSimon Glass
This report is normally generated by U-Boot proper. Correct the condition here so that it respects the Kconfig options for bootstage. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Don't set up MTRRs in SPLSimon Glass
The MTRRs are normally set up in U-Boot proper, so avoid setting them up in SPL as well. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Support TPL in Intel common codeSimon Glass
Update the Makefie rules to ensure that the correct files are built when TPL is being used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: broadwell: Implement PCH_REQ_PMBASE_INFOSimon Glass
Implement this ioctl() to support power off. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: ivybridge: Implement PCH_REQ_PMBASE_INFOSimon Glass
Implement this ioctl() to support power off. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: mrccache: Add more debuggingSimon Glass
When the MRC cache fails to save it is useful to have some debugging info to indicate what when wrong. Add some more debug() calls. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Support saving MRC data from SPLSimon Glass
When SPL is used to set up the memory controller we want to save the MRC data in SPL to avoid needing to pass it up to U-Boot proper to save. Add a function to handle that. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Add common Intel code for SPLSimon Glass
Add an implementation of arch_cpu_init_f() so that the x86 SPL code builds and identifies the CPU. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: broadwell: Select refcode and CPU code for SPLSimon Glass
Allow broadwell to build for SPL and include the reference code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: broadwell: Allow booting from SPLSimon Glass
At present broadwell only supports booting straight into U-Boot proper. Add a separate init file to boot from SPL into U-Boot proper, and select it when SPL is in use. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Allow 16-bit init to be in TPLSimon Glass
At present we support having 16-bit init be in SPL or U-Boot proper, but not TPL. Add support for this so that TPL can boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Add support for starting from SPL/TPLSimon Glass
When a previous phase of U-Boot has run we need to adjust the init of subsequent states to avoid messing up the CPU state. Add a new version of the start logic for SPL, when it boots from TPL (start_from tpl.c) and a new version for U-Boot when it boots from SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: broadwell: Split CPU initSimon Glass
Split the CPU init into two parts - the 'full' init which happens in the first U-Boot phase, and the rest of the init that happens on subsequent stages. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: broadwell: Move init of debug UART to cpu.cSimon Glass
At present the debug UART is set up in sdram.c which is not the best place since it has nothing in particular to do with SDRAM. Since we want to support initing this in SPL too, move it to a common file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: added 'broadwell' tag in the commit title] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: broadwell: Allow SDRAM init from SPLSimon Glass
At present, for broadwell, SDRAM is always set up in U-Boot proper since the 64-bit mode (which uses SDRAM init in SPL) is not supported. Update the code to allow SDRAM init in SPL instead so that U-Boot proper can be loaded into SDRAM and run from there. This allows U-Boot to be compressed to reduce space, since it is not necessary to run it directly from flash. It could later allow us to support 64-bit U-Boot on broadwell. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit (git 2.34.1) at 2025-02-07 10:47:47 +0000