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Now that we have added MRC cache for Intel FSP and BayTrail codes,
enable it for all BayTrail boards (Bayley Bay and Minnow Max).
Note it turns out that FSP for Intel Atom E6xx does not produce
the HOB for NV storage, so we don't have such functionality on
Intel Crown Bay board.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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Save MRC cache to SPI flash in arch_misc_init().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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fsp_init() call has a parameter nvs_buf which is used by FSP as the
MRC cache but currently is blindly set to NULL. Retreive the MRC
cache from SPI flash and pass it to fsp_init() call. After the call,
save FSP produced MRC cache to SPI flash too.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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Currently struct fmap_entry is used to describe a mrc region.
However this structure contains some other fields that are not
related to mrc cache and causes confusion. Besides, it does not
include a base address field to store SPI flash's base address.
Instead in the mrccache.c it tries to use CONFIG_ROM_SIZE to
calculate the SPI flash base address, which unfortunately is
not 100% correct as CONFIG_ROM_SIZE may not match the whole
SPI flash size.
Define a new struct mrc_region and use it instead.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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Remove the call to custom mrc cache APIs, and use the ones
provided in the mrccache lib.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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This adds mrccache_reserve(), mrccache_get_region() and
mrccache_save() APIs to the mrccache codes. They are ported
from the ivybridge implementation, but with some changes.
For example, in the mrccache_reserve(), ivybridge version
only reserves the pure MRC data, which causes additional
malloc() when saving the cache as the save API needs some
meta data. Now we change it to save the whole MRC date plus
the meta data to elinimate the need for the malloc() later.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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Fix some nits, improve some comments and reorder some codes
a little bit.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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For the cache record to write in mrccache_update(), we should
perform a sanity test to see if it is a valid one.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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mrccache implementation can be common for all boards. Move it
from ivybridge cpu directory to the common lib directory.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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Create a Kconfig option for enabling MRC cache.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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It would be helpful to have a command to show FSP header. So far
it only supports FSP header which conforms to FSP spec 1.0.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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Introduce a new fsp command and make the existing hob command a
sub-command to fsp for future extension. Also move cmd_hob.c to
the dedicated fsp sub-directory in arch/x86/lib.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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When examining a HOB, it's useful to see which GUID this HOB
belongs to. Add GUID output in the hob command to aid this.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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Compact hob command output, especially by making hob type string a
little bit shorter so that we can leave room for future extension.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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System Management BIOS (SMBIOS) is a specification for how
motherboard and system vendors present management information
about their products in a standard format by extending the BIOS
interface on Intel architecture systems. As of today the latest
spec is 3.0 and can be downloaded from DMTF website. This commit
adds a simple and minimum required implementation.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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install_e820_map() has nothing to do with zimage related codes.
Move it to a dedicated place.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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Some OS (like VxWorks) requires GDT entry 1 to be the 32-bit CS.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Jian Luo <jian.luo4@boschrexroth.de>
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Add a Kconfig option to disable the Integrated Graphics Device (IGD)
so that it does not show in the PCI configuration space as a VGA
disaplay controller. This gives a chance for U-Boot to run PCI/PCIe
based graphics card's VGA BIOS and use that for the graphics console.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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Remove bd82x6x_pci_bus_enable_resources() that is not called anywhere.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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This patch enables DM_SERIAL for all ARCH_MVEBU boards (AXP & A38x).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Luka Perkov <luka.perkov@sartura.hr>
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This patch adds driver model support for some Marvell MVEBU SoC's. Including
Armada XP and 38x. All 3 currently mainlined boards are converted. DM is now
selected automatically for MVEBU platforms.
With this DM support now available for MVEBU, hardcoding the base addresses
and other information is not necessary any more. Probing should be done
by using the values provided via the device tree now instead. For this
the driver also need to be converted to DM. Patches for some of the drivers
will follow.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Luka Perkov <luka.perkov@sartura.hr>
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These will be needed by the upcoming DM (driver model) support for
the Armada XP / 38x SoC's. This will provide DT based probing.
The dts files are copied 1:1 from the Linux kernel release v4.2.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
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Instead of calling board_init_r() directly from board_init_f(), just
return from board_init_f(). This will make the code continue executing
in crt0.S _main(), from which the board_init_r() is called. This patch
aligns the MVEBU SPL with the correct SPL design as well as reduces
the stack utilisation slightly.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Luka Perkov <luka.perkov@sartura.hr>
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When running on the AXP I sometimes noticed a strange behavior. As some
characters are not echoed on the U-Boot prompt. Not disabling the
lowlevel_init code, especially calling cpu_init_cp15() in the main
U-Boot seems to solve this issue.
Signed-off-by: Stefan Roese <sr@denx.de>
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This patch enables the use of the kwboot tool, to boot mainline U-Boot
on the Marvell Armada XP/38x SoC's. This is done by returning to the
SoC's BootROM after SPL has initialized the SDRAM. We need to make sure
to not reconfigure the internal register space and MBARs. Otherwise
the BootROM will not be able to continue after SPL jumps back to it.
To use this feature, please don't forget to change the BOOT_FROM line
in your board specfic kwbimage.cfg file this way:
BOOT_FROM uart
Tested on these Marvell eval boards:
DB-MV784MP-GP - Armada XP
DB-88F6820-GP - Armada 38x
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Dirk Eibach <eibach@gdsys.de>
Cc: Kevin Smith <kevin.smith@elecsyscorp.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
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The C.H.I.P. is a small SBC with an Allwinner R8, 8GB of NAND, 512MB of
RAM, USB host and OTG, a wifi / bluetooth combo chip, an audio/video jack
and two connectors to plug additional boards on top of it.
The DT is identical to the DT submitted to the upstream kernel.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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Linux had a number of changes to the AXP209 DTSI. Sync ours.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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Add the latest kernel changes to the sun5i family DTSI.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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So far, even if CONFIG_MMC was not enabled the board code was trying to use
the MMC-related functions, resulting in linker errors.
Protect those calls by an ifdef.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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The Sinovoip BPI-M2 is a SBC board based on the A31s SoC it features
1G RAM, a microsd slot, Gbit ethernet, 4 usb-a USB-2 ports, ir receiver,
stereo headphone jack and hdmi video output.
The dts changes are identical to the dts files submitted upstream.
A few notes on the use if dldo and aldo regulators. DLDO1 is used
for Vdd for the ethernet phy, ALDO2 is used for AVdd for the ethernet
phy. ALDO1 is used to power the sdio wifi module.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
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Stop prefixing the axp functions for setting voltages, etc. with the
model number, there ever is only one pmic driver built into u-boot,
this allows simplifying the callers.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
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We now have generic q8_a?3_defconfig files for Q8 formfactor tablets with
an A13 / A23 / A33 SoC, there is no need for these PCB variant specific
defconfig-s and they only serve to confuse the user.
Note that in case of the forfun_q88db_defconfig and TZX-Q8-713B7_defconfig
for A13 based Q8 tablets there is not even a dts file for these in the
upstream kernel, which is all the more reason to remove them.
The generic q8_a?3_defconfig files have been tested on an Et_q8_v1_6,
Ippo_q8h_v1_2_a33_1024x600, Ippo_q8h_v1_2 and TZX-Q8-713B7 tablet, and the
forfun_q88db_defconfig is identical to q8_a13_tablet_defconfig.
This leaves only the Ippo_q8h_v5 untested with the new generic defconfigs
but there is no reason to assume that it will not work.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
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common/dlmalloc.c is quite big, both in .text and .data usage. E.g. for a
Mele_M9 sun6i board build this reduces .text from 0x4214 to 0x3b94 bytes,
and .data from 0x54c to 0x144 bytes.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Tom Rini <trini@konsulko.com>
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Select CONFIG_SPL_STACK_R for sunxi boards, this gives us much more
room on the stack once we've the DRAM running.
Besides being a good change to have on itself, this also paves the
way for switching to using malloc_simple in the SPL which cuts of
close to 4KiB of the SPL size.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
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Introduce a mach-mvebu/Kconfig for all Armada based SoC's.
Signed-off-by: Stefan Roese <sr@denx.de>
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This code is no-longer used. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Seen this one in the wild. Is labelled "Raspberry Pi Model A+ V1.1,
(C) Raspberry Pi 2014". A standard A+ board, much like the one with
version 0x12, didn't notice any differencies.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
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On keystone2 Lamarr and Edison platforms, the PA clocksource
mux in PLL REG1, can be changed only after enabling its clock
domain.
So selecting the output of PASS PLL as input to PA only after
enabling the clockdomain.
This is as per the debug done by "Vitaly Andrianov <vitalya@ti.com>"
and based on the previous work done by "Hao Zhang <hzhang@ti.com>"
Fixes: d634a0775bcf ("ARM: keystone2: Cleanup PLL init code")
Reported-by: Vitaly Andrianov <vitalya@ti.com>
Tested-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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There are various toolchain issues that cause us to produce invalid
binaries with certain gcc 4.8.x and 4.9.x versions when we don't pass
this flag in.
Tested-by: Joakim Tjernlund <joakim.tjernlund@transmode.se>
Signed-off-by: Tom Rini <trini@konsulko.com>
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We need "u-boot,dm-pre-reloc" in the socfpga_cyclone5_socdk.dts file in
order for the SPL to use SD/MMC.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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Update the L2 AUX CTRL settings for the SoCFPGA.
Enabling D and I prefetch bits helps improve SDRAM performance on the
platform.
Also, we need to enable bit 22 of the L2. By not having bit 22 set in the
PL310 Auxiliary Control register (shared attribute override enable) has the
side effect of transforming Normal Shared Non-cacheable reads into Cacheable
no-allocate reads.
Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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Add 'volatile' qualifier to the asm statement in get_cr()
so that the statement is not optimized out by the compiler.
(http://comments.gmane.org/gmane.linux.linaro.toolchain/5163)
Without the 'volatile', get_cr() returns a wrong value which
prevents enabling the MMU and later causes a PCIE VA access
failure.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
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PCI driver currently hangs on mx6qp.
Toggle the reset bit with the appropriate timings to fix the issue.
Based on the FSL kernel driver implementation.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
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Initialize all GICD_IGROUPRn registers and set up GICC_CTLR to enable
interrupts to the primary CPU. This fixes issues seen after booting a
Linux kernel from U-Boot.
Suggested-by: Marc Zyngier <marc.zyngier@arm.com>
Suggested-by: Mark Rutland <mark.rutland@arm.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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For EL3 and EL2, the documentation says that bits 31 and 23 are reserved
but should be written as 1.
For EL1, only bit 23 is not reserved, so only write bit 31 as 1.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Use the inner shareable attribute for memory, which makes more sense
considering that this code is called when caches are being enabled.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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