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2015-02-02Merge branch 'master' of git://git.denx.de/u-boot-tiTom Rini
2015-02-02Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini
2015-02-02sunxi: rsb: Move rsb_set_device_mode() call to rsb_init()Hans de Goede
It turns out that the device_mode_data is rsb specific, rather then slave specific, so integrate the rsb_set_device_mode() call into rsb_init(). Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-02-02sunxi: rsb: Add sun9i (A80 support)Hans de Goede
Add support for the A80 to the rsb code. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-02-02sunxi: Add a GMAC Transmit Clock Delay Chain Kconfig optionHans de Goede
And use this to set the GMAC Transmit Clock Delay Chain value on Banana boards, rather then keying of CONFIG_TARGET_FOO. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-31Merge branch 'patman' of git://git.denx.de/u-boot-x86Tom Rini
2015-01-30sandbox: Add a -D option to use a default device treeSimon Glass
It is painful to specify the full path to the device tree with the -d option. It is normally kept in the same directory as U-Boot, so provide an option to use this by default. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-30sandbox: Correct cros-ec keyboard definitionSimon Glass
The other boards got updated to the standard binding. Update sandbox as well. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-30Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini
2015-01-30Merge branch 'master' of git://git.denx.de/u-boot-dmTom Rini
2015-01-30ARM: armv7 fix spelling of SCTRLPeng Fan
SCTLR is the abbreviation of System Control Register, so we should use SCTLR but not SCTRL. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-01-30vexpress64: support the Juno Development PlatformLinus Walleij
The Juno Development Platform is a physical Versatile Express device with some differences from the emulated semihosting models. The main difference is that the system is split in a SoC and an FPGA where the SoC hosts the serial ports at totally different adresses. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-30vexpress64: get rid of CONFIG_SYS_EXTRA_OPTIONSLinus Walleij
The Versatile Express ARMv8 semihosted FVP platform is still using the legacy CONFIG_SYS_EXTRA_OPTIONS method to configure some compile-time flags. Get rid of this and create a Kconfig entry for the FVP model, and a selectable bool for the semihosting library. The FVP subboard is now modeled as a target choice so we can eventually choose between different ARMv8 versatile express boards (FVP, base model, Juno...) this way. All dependent symbols are updated to reflect this. The 64bit Versatile Express board symbols are renamed VEXPRESS64 so we have some chance to see what is actually going on. Tested on the FVP fast model. Acked-by: Steve Rae <srae@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-30MIPS: unify CPU code in arch/mips/cpu/Daniel Schwierzeck
Unify and move code in arch/mips/cpu/mips[32|64]/ to arch/mips/cpu/. The CPU specific config.mk files need to remain until CONFIG_STANDALONE_LOAD_ADDR is converted to a global Kconfig symbol. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-30MIPS: move au1x00 SoC code to arch/mips/mach-au1x00Daniel Schwierzeck
Move all au1x00 code out of arch/mips/cpu/mips32 to allow unification of CPU code in a later patch. The reorganization of the SoC specific header files will be done in a later patch series. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com>
2015-01-30MIPS: handle mips64 ST0_KX bit in mips32 start.SPaul Burton
In preparation for sharing a single copy of start.S between mips32 & mips64, handle setting the KX bit of the cop0 Status register when the mips32 start.S is built for mips64. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-30MIPS: handle mips64 relocs in mips32 start.SPaul Burton
In preparation for sharing a single copy of start.S between mips32 & mips64, handle mips64 relocations in the mips32 start.S when built for mips64. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-30MIPS: use asm.h macros in mips32 start.SPaul Burton
Where the mips32 & mips64 implementations of start.S differ in terms of access sizes & offsets, use the appropriate macros from asm.h to abstract those differences away. This is in preparation for sharing a single copy of start.S between mips32 & mips64. The exception to this is loads of immediates to be written to the cop0 Config register, which is a 32bit register on mips64 and therefore constants written to it can be loaded as such. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-29dm: exynos: dts: Set the offset length for cros_ecSimon Glass
The EC has no concept of offset, so use a value of 0. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-29odroid u3: dts: add missing i2c aliasesPrzemyslaw Marczak
This change fixes i2c bus numbering for Odroid U3. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com>
2015-01-29exynos5: pinmux: check flag for i2c configPrzemyslaw Marczak
Some versions of Exynos5 supports High-Speed I2C, on few interfaces, this change allows support this. The new flag is: PINMUX_FLAG_HS_MODE Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Akshay Saraswat <akshay.s@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-01-29arndale: dts: add missing i2c aliasesPrzemyslaw Marczak
Without this alias setting, the seq numbers of the i2c devices are wrong. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com>
2015-01-29exynos4: dts: add missing i2c propertiesPrzemyslaw Marczak
This patch modify i2c nodes in exynos4.dtsi with: - adding proper interrupts arrays for each i2c node, which allows to decode periph id - add reg address for each i2c node for i2c driver internal use Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com>
2015-01-29Export redesignMartin Dorwig
this is an atempt to make the export of functions typesafe. I replaced the jumptable void ** by a struct (jt_funcs) with function pointers. The EXPORT_FUNC macro now has 3 fixed parameters and one variadic parameter The first is the name of the exported function, the rest of the parameters are used to format a functionpointer in the jumptable, the EXPORT_FUNC macros are expanded three times, 1. to declare the members of the struct 2. to initialize the structmember pointers 3. to call the functions in stubs.c Signed-off-by: Martin Dorwig <dorwig@tetronik.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> (resending to the list since my tweaks are not quite trivial)
2015-01-29dm: i2c: Provide an offset length parameter where neededSimon Glass
Rather than assuming that the chip offset length is 1, allow it to be provided. This allows chips that don't use the default offset length to be used (at present they are only supported by the command line 'i2c' command which sets the offset length explicitly). Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
2015-01-29dm: exynos: dts: Use GPIO bank phandles for GPIOsSimon Glass
U-Boot now supports using GPIOs using bank phandles instead of global numbers. Update the exynos device tree files to use this. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
2015-01-29dm: tegra: dts: Use TEGRA_GPIO() macro for all GPIOsSimon Glass
This new method is much easier and matches the kernel. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-29dm: mmc: Remove use of fdtdec GPIO supportSimon Glass
These functions are going away, so use the new uclass support instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-29dm: zynq: Remove inline gpio functionsSimon Glass
These functions serve no useful purpose, and conflict with the generic API. Drop them. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-29dm: tegra: video: Remove use of fdtdec GPIO supportSimon Glass
These functions are going away, so use the new uclass support instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-29dm: demo: Add a simple GPIO demonstrationSimon Glass
Add a new 'demo light' command which uses GPIOs to control imaginary lights. Each light is assigned a bit number in the overall value. This provides an example driver for using the new GPIO API. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-29davinci: Do not duplicate setting of gdTom Rini
In f0c3a6c we stopped setting gd in board_init_f, but later had to revert to due problems on certain platforms. As davinci does not look to have these problems, we can drop the setting here and rely upon crt0.S to do it. Cc: Peter Howard <pjh@northern-ridge.com.au> Signed-off-by: Tom Rini <trini@ti.com>
2015-01-29omap3: add some MUX definitions for upcoming cairoAlbert ARIBAUD \(3ADEV\)
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
2015-01-29omap3: mmc: add 1.8v bias setting for MMC1Albert ARIBAUD \(3ADEV\)
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
2015-01-29omap3: add SDRC settings for Samsung K4X51163PGAlbert ARIBAUD \(3ADEV\)
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
2015-01-29omap3: make SDRC SHARING setting configurableAlbert ARIBAUD \(3ADEV\)
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
2015-01-29omap3: enable GP9 timer and UART2Albert ARIBAUD \(3ADEV\)
These are needed for the upcoming Cairo board support. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
2015-01-29ARM: OMAP5: DRA7xx: Add support for power rail groupingLubomir Popov
On the DRA72x (J6Eco) EVM one PMIC SMPS is powering three SoC core rails. This concept of using one SMPS to supply multiple core domains (in various, although limited combinations, per primary device use case) has now become common and is used by many customer J6/J6Eco designs; it is supported by a number of corresponding PMIC OTP versions. This patch implements correct operation of the core voltages scaling routine by ensuring that each SMPS that is supplying more than one domain shall be written only once, and with the highest voltage of those fused in the SoC (or of those defined in the corresponding header if fuse read is disabled or fails) for the power rails belonging to the group. The patch also replaces some PMIC-related magic numbers with the appropriate definitions. The default OPP_NOM voltages for the DRA7xx SoCs are updated as well, per the latest DMs. Signed-off-by: Lubomir Popov <l-popov@ti.com>
2015-01-29malta: IDE supportPaul Burton
This patch adds IDE support to the MIPS Malta board. The IDE controller is enabled after probing the PCI bus and otherwise just makes use of U-boot generic IDE support. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-29MIPS: clear TagLo select 2 during cache initPaul Burton
Current MIPS cores from Imagination Technologies use TagLo select 2 for the data cache. The architecture requires that it is safe for software to write to this register even if it isn't present, so take the trivial option of clearing both selects 0 & 2. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-29MIPS: allow systems to skip loads during cache initPaul Burton
Current MIPS systems do not require that loads be performed to force the parity of cache lines, a simple invalidate by clearing the tag for each line will suffice. Thus this patch makes the loads & subsequent second invalidation conditional upon the CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD option, and defines that for existing mips32 targets. Exceptions are malta where this is known to be unnecessary, and qemu-mips where caches are not implemented. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-29MIPS: inline mips_init_[id]cache functionsPaul Burton
The mips_init_[id]cache functions are small & only called once from a single callsite. Inlining them allows mips_cache_reset to avoid having to bother moving arguments around & leaves it a leaf function which is thus able to simply keep the return address live in the ra register throughout, simplifying the code. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-29MIPS: refactor cache loops to a macroPaul Burton
Reduce duplication by performing loops through cache tags using an assembler macro. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-29MIPS: refactor L1 cache config reads to a macroPaul Burton
Reduce duplication between reading the configuration of the L1 dcache & icache by performing both using a macro which calculates the appropriate line & cache sizes from the coprocessor 0 Config1 register. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-29MIPS: unify cache initialization codePaul Burton
The mips32 & mips64 cache initialization code differs only in that the mips32 code supports reading the cache size from coprocessor 0 registers at runtime. Move the more developed mips32 version to a common arch/mips/lib/cache_init.S & remove the now-redundant mips64 version in order to reduce duplication. The temporary registers used are shuffled slightly in order to work for both mips32 & mips64 builds. The RA register is defined differently to suit mips32 & mips64, but will be removed by a later commit in the series after further cleanup. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-29MIPS: unify cache maintenance functionsPaul Burton
Move the more developed mips32 version of the cache maintenance functions to a common arch/mips/lib/cache.c, in order to reduce duplication between mips32 & mips64. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-29MIPS: avoid .set ISA for cache operationsPaul Burton
As a step towards unifying the cache maintenance code for mips32 & mips64 CPUs, stop using ".set <ISA>" directives in the more developed mips32 version of the code. Instead, when present make use of the GCC builtin for emitting a cache instruction. When not present, simply don't bother with the .set directives since U-boot always builds with -march=mips32 or higher anyway. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-26Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini
2015-01-26Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini
2015-01-26Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblazeTom Rini