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2011-09-30omap-common/omap4: relocate early UART clock setupSimon Schwarz
Moves the early UART clock setup setup_clocks_for_console() from preloader_console_init() to s_init() of OMAP4. This is done to prepare for OMAP3 integration. This patch was posted seperatly to the mailinglist but I decidet - since it is a prereqesit for this patch to add it. Former port to ML: http://article.gmane.org/gmane.comp.boot-loaders.u-boot/104395 Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com> Signed-off-by: Tom Rini <trini@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30OMAP3: Overo: Update GPMC timing for ethernet chipPhilip Balister
The existing timing does not quite meet the minimum requirements in the LAN9221 datasheet. The timing in this patch solves problems noticed on some parts. The patch also combines the CS configuration for the overo and igep0020 boards per request. Signed-off-by: Philip Balister <philip@opensdr.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30Armada100: Enable Ethernet support for GplugDAjay Bhargav
This patch enables ethernet support for Marvell GplugD board. Network related commands works. Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
2011-09-30net: Adds Fast Ethernet Controller driver for Armada100Ajay Bhargav
This patch adds support for Fast Ethernet Controller driver for Armada100 series. Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
2011-09-30gpio: Add GPIO driver for Marvell SoC Armada100Ajay Bhargav
This patch adds support for generic GPIO driver framework for Marvell SoC Armada100. Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
2011-09-29powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driverYork Sun
Unified DDR driver is maintained for better performance, robustness and bug fixes. Upgrading to use unified DDR driver for MPC83xx takes advantage of overall improvement. It requires changes for board files to customize platform-dependent parameters. To utilize the unified DDR driver, a board needs to define CONFIG_FSL_DDRx in the header file. No more boards will be accepted without such definition. Note: the workaround for erratum DDR6 for the very old MPC834x Rev 1.0/1.1 and MPC8360 Rev 1.1/1.2 parts is not migrated to unified driver. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29powerpc/mpc8xxx: Add DDR2 to unified DDR driverYork Sun
DDR2 has different ODT table and values. Adding table according to Samsung application note. Fix additive latency calculation to avoid interger underflow. Also converted typedef dynamic_odt_t to struct dynamic_odt. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29powerpc/mpc8xxx: Fix picos_to_mclk() and get_memory_clk_period_ps()York Sun
Reduce the calculation error to 1ps. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29powerpc/mpc8xxx: Add SPD EEPROM address for single controller 2 slotsYork Sun
The two slots on the same controller have different addresses. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_enYork Sun
Check second DIMM slot in case the first one is empty. Honor DQS enable option for SDRAM mode register. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29powerpc/mpc8xxx: Move DDR RCW overriding to common codeYork Sun
DDR RCW varies at different speeds. It is common for all platform. Move it out from corenet_ds. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29powerpc/mpc8xxx: Extend CWL tableYork Sun
Extend CAS write Latency (CWL) table to comply with DDR3 spec Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29powerpc/85xx: Cleanup how SVR_MAJ() is defined on MPC8536Kumar Gala
The MPC8536 seems to use only 3 bits for the major revision field in the SVR rather than the 4 bits used by all other processors. The most significant bit is used as a mfg code on MPC8536. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29powerpc/85xx: Add networking support to P1023RDSRoy Zang
The P1023 has two 1G ethernet controllers the first can run in SGMII, RGMII, or RMII. The second can only do SGMII & RGMII. We need to setup a for SoC & board registers based on our various configuration for ethernet to function properly on the board. Removed CONFIG_SYS_FMAN_FW as its not used anywhere. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29powerpc/85xx: Add support for FMan ethernet in Independent modeKumar Gala
The Frame Manager (FMan) on QorIQ SoCs with DPAA (datapath acceleration architecture) is the ethernet contoller block. Normally it is utilized via Queue Manager (Qman) and Buffer Manager (Bman). However for boot usage the FMan supports a mode similar to QE or CPM ethernet collers called Independent mode. Additionally the FMan block supports multiple 1g and 10g interfaces as a single entity in the system rather than each controller being managed uniquely. This means we have to initialize all of Fman regardless of the number of interfaces we utilize. Different SoCs support different combinations of the number of FMan as well as the number of 1g & 10g interfaces support per Fman. We add support for the following SoCs: * P1023 - 1 Fman, 2x1g * P4080 - 2 Fman, each Fman has 4x1g and 1x10g * P204x/P3041/P5020 - 1 Fman, 5x1g, 1x10g Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Dai Haruki <dai.haruki@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29powerpc/mp: add support for discontiguous coresTimur Tabi
Some SOCs have discontiguously-numbered cores, and so we can't determine the valid core numbers via the FRR register any more. We define CPU_TYPE_ENTRY_MASK to specify a discontiguous core mask, and helper functions to process the mask and enumerate over the set of valid cores. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29fdt: Rename fdt_create_phandle to fdt_set_phandleKumar Gala
The old fdt_create_phandle didn't actually create a phandle it just set one. We'll introduce a new helper that actually does creation. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Gerald Van Baren <vanbaren@cideas.com>
2011-09-29powerpc/85xx: Fix compile warnings/errors if CONFIG_SYS_DPAA_FMAN isn't setKumar Gala
Add ifdef protection around fman specific code related to device tree clock setup. If we dont have CONFIG_SYS_DPAA_FMAN defined we shouldn't be executing this code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010)Poonam Aggrwal
Issue: Address masking doesn't work properly. When sum of the base address, defined by BA, and memory bank size, defined by AM, exceeds 4GB (0xffff_ffff) then AMASKn[AM] doesn't mask CSPRn[BA] bits. Impact: This will impact booting when we are reprogramming CSPR0(BA) and AMASK0(AMASK) while executing from NOR Flash. Workaround: Re-programming of CSPR(BA) and AMASK is done while not executing from NOR Flash. The code which programs the BA and AMASK is executed from L2-SRAM. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29powerpc/P1010: Add workaround for erratum P1010-A003549 (related to IFC)Poonam Aggrwal
Issue: Peripheral connected to IFC_CS3 may hamper booting from IFC. Impact: Boot from IFC may not be successful if IFC_CS3 is used. Workaround: If IFC_CS3 is used, gate IFC_CS3 while booting from NAND or NOR. Also Software should select IFC_CS3 using PMUXCR[26:27] = 0x01. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29fsl_ifc: Add the workaround for erratum IFC-A002769 (enable on P1010)Poonam Aggrwal
Issue: The NOR-FCM does not support access to unaligned addresses for 16 bit port size Impact: When 16 bit port size is used, accesses not aligned to 16 bit address boundary will result in incorrect data Workaround: The workaround is to switch to GPCM mode for NOR Flash access. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29powerpc/85xx: Expanding the window of CCSRBAR in AS=1 from 4k to 1MPoonam Aggrwal
For an IFC Erratum (A-003399) we will need to access IFC registers in cpu_init_early_f() so expand the TLB covering CCSR to 1M. Since we need a TLB to cover 1M we move to using TLB1 array for all the early mappings so we can cover various sizes beyond 4k. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29nand: Freescale Integrated Flash Controller NAND supportDipen Dudhat
Add NAND support (including spl) on IFC, such as is found on the p1010. Note that using hardware ECC on IFC with small-page NAND (which is what comes on the p1010rdb reference board) means there will be insufficient OOB space for JFFS2, since IFC does not support 1-bit ECC. UBI should work, as it does not use OOB for anything but ECC. When hardware ECC is not enabled in CSOR, software ECC is now used. Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> [scottwood@freescale.com: ECC rework and misc fixes] Signed-off-by: Scott Wood <scottwood@freescale.com>
2011-09-29powerpc/85xx: relocate CCSR before creating the initial RAM areaTimur Tabi
Before main memory (DDR) is initialized, the on-chip L1 cache is used as a memory area for the stack and the global data (gd_t) structure. This is called the initial RAM area, or initram. The L1 cache is locked and the TLBs point to a non-existent address (so that there's no chance it will overlap main memory or any device). The L1 cache is also configured not to write out to memory or the L2 cache, so everything stays in the L1 cache. One of the things we might do while running out of initram is relocate CCSR. On reset, CCSR is typically located at some high 32-bit address, like 0xfe000000, and this may not be the best place for CCSR. For example, on 36-bit systems, CCSR is relocated to 0xffe000000, near the top of 36-bit memory space. On some future Freescale SOCs, the L1 cache will be forced to write to the backing store, so we can no longer have the TLBs point to non-existent address. Instead, we will point the TLBs to an unused area in CCSR. In order for this technique to work, CCSR needs to be relocated before the initram memory is enabled. Unlike the original CCSR relocation code in cpu_init_early_f(), the TLBs we create now for relocating CCSR are deleted after the relocation is finished. cpu_init_early_f() will still need to create a TLB for CCSR (at the new location) for normal U-Boot purposes. This is done to keep the impact to existing U-Boot code minimal and to better isolate the CCSR relocation code. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macrosTimur Tabi
Introduce the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW macros, which contain the high and low portions of CONFIG_SYS_CCSRBAR_PHYS. This is necessary for the assembly-language code that relocates CCSR, since the assembler does not understand 64-bit constants. CONFIG_SYS_CCSRBAR_PHYS is automatically defined from the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW macros, so it should not be defined in a board header file. Similarly, CONFIG_SYS_CCSRBAR_DEFAULT is defined for each SOC in config_mpc85xx.h, so it should also not be defined in the board header file. CONFIG_SYS_CCSR_DO_NOT_RELOCATE is a "short-cut" macro that guarantees that CONFIG_SYS_CCSRBAR_PHYS is set to the same value as CONFIG_SYS_CCSRBAR_DEFAULT, and so CCSR will not be relocated. Since CONFIG_SYS_CCSRBAR_DEFAULT is locked to a fixed value, multi-stage U-Boot builds (e.g. NAND) are required to relocate CCSR only during the last stage (i.e. the "real" U-Boot). All other stages should define CONFIG_SYS_CCSR_DO_NOT_RELOCATE to ensure that CCSR is not relocated. README is updated with descriptions of all the CONFIG_SYS_CCSRBAR_xxx macros. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29powerpc/85xx: Enable internal USB UTMI PHY on p204x/p3041/p50x0Kumar Gala
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29powerpc/85xx: Add ULPI and UTMI USB Phy support for P1010/P1014Ramneek Mehresh
Add UTMI and ULPI PHY support for USB controller on qoriq series of processors with internal UTMI PHY implemented, for example P1010/P1014 - Use both getenv() and hwconfig to get USB phy type till getenv() is depricated - Introduce CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY to specify if soc has internal UTMI phy Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Acked-by: Remy Bohmer <linux@bohmer.net> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29Blackfin: uart: implement loop callback for postMike Frysinger
This allows the Blackfin UART driver to be tested via post. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-09-29Blackfin: post: generalize led/button tests with GPIOsMike Frysinger
Make it easy for any Blackfin board to enable led/push button tests. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-09-29Blackfin: post: drop custom test listMike Frysinger
The few tests that are Blackfin-specific have been migrated to common code or been rewritten with the existing "bsp-specific" defines. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-09-19ppc4xx: Flush dcache after DDR2 autocalibration with caches onStefan Roese
Flush the dcache before removing the TLB with caches enabled. Otherwise this might lead to problems later on, e.g. while booting Linux (as seen on ICON-440SPe). Signed-off-by: Stefan Roese <sr@denx.de>
2011-09-19Fix incorrect array size of phy settings for 405EXWeirich, Bernhard
Change bd_t->bi_phy* arrays from 1 to 2 for PPC405EX since 405EX has 2 ethernet interfaces. Signed-off-by: Bernhard Weirich <bernhard.weirich@riedel.net> Signed-off-by: Stefan Roese <sr@denx.de>
2011-09-13led: remove camel casing of led identifiers globallyJason Kridner
Result of running the following command to address Wolfgang's comment about camel case: for file in `find . | grep '\.[chS]$'`; do perl -i -pe 's/(green|yellow|red|blue)_LED_(on|off)/$1_led_$2/g' $file; done Discussion: http://patchwork.ozlabs.org/patch/84988/ Signed-off-by: Jason Kridner <jkridner@beagleboard.org> Signed-off-by: Joel A Fernandes <agnel.joel@gmail.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-13omap4: IO settingsAneesh V
Tuning some IO settings for better performance and power. And consolidate all such IO settings at one place. Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-13omap4: make SDRAM init work for ES1.0 siliconAneesh V
SDRAM init was not working on ES1.0 due to a programming error. A pointer that was passed by value to a function was set in function emif_get_device_details(), but the effect wouldn't be seen in the calling function. The issue came out while testing for ES1.0 because ES1.0 doesn't have any SDRAM chips connected to CS1 Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-13omap: gpio: generic changes after changing APISanjeev Premi
This patch contains the generic changes required after change to generic API in the previous patch. Signed-off-by: Sanjeev Premi <premi@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-13omap: gpio: Use generic APISanjeev Premi
Convert all OMAP specific functions to use the common API definitions in include/asm/gpio.h. In the process, made few additional changes: - Use -EINVAL consistently. -1 was used in many places. - Removed one-liner static functions that were used only once. Replaced the content as necessary. - Combines implementation of functions omap_get_gpio_dataout() and omap_get_gpio_datain(). To do so, new static function _get_gpio_direction() was added. Signed-off-by: Sanjeev Premi <premi@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-12ARMV7: OMAP3: Add 37xx ESx revision numbers.Howard D. Gray
OMAP3: Add 37xx ESx revision numbers. Signed-off-by: Michael Jones <michael.jones@matrix-vision.de> Signed-off-by: Howard D. Gray <howard.gray@matrix-vision.de> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-12OMAP: Add function to get state of a GPIO outputJoel A Fernandes
Read directly from OMAP_GPIO_DATAOUT to get the output state of the GPIO pin Signed-off-by: Joel A Fernandes <agnel.joel@gmail.com> Signed-off-by: Jason Kridner <jkridner@beagleboard.org> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-11Minor coding style cleanup.Wolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-09-10tegra2: fix warning: "assert" redefinedWolfgang Denk
Commit 21726a7 "Add assert() for debug assertions" caused build warnings for all tegra2 based boards: clock.c:36:1: warning: "assert" redefined In file included from clock.c:29: include/common.h:144:1: warning: this is the location of the previous definition Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Simon Glass <sjg@chromium.org>
2011-09-10KS8695: move TIMER_ definitions before code useGreg Ungerer
Move the TIMER_ definitions before they are used in KS8695 timer.c code. Fixes: timer.c: In function ‘timer_init’: timer.c:37: error: ‘TIMER_COUNT’ undeclared (first use in this function) timer.c:37: error: (Each undeclared identifier is reported only once timer.c:37: error: for each function it appears in.) timer.c:38: error: ‘TIMER_PULSE’ undeclared (first use in this function) Signed-off-by: Greg Ungerer <greg.ungerer@opengear.com>
2011-09-07PXA: FIX: Deep-sleep return address in stored in PSPRMarek Vasut
FIX for a typo-bug: The address is stored in PSPR, not PSSR. Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
2011-09-07MX31: fix missing mxc_get_clk() callStefano Babic
Add missing case to be used in common MXC code. Signed-off-by: Stefano Babic <sbabic@denx.de>
2011-09-07omap24xx: fix 'reset_timer_masked' declaration errorWolfgang Denk
Commit 17659d7 "Timer: Remove reset_timer_masked()" introduced a static declaration for reset_timer_masked() which causes build errors: timer.c:45: error: static declaration of 'reset_timer_masked' follows non-static declaration include/asm/u-boot-arm.h:70: error: previous declaration of 'reset_timer_masked' was here Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Graeme Russ <graeme.russ@gmail.com> Cc: Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-07ARM: remove broken "impa7" board.Wolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Marius Gröger <mag@sysgo.de>
2011-09-07ARM: remove broken "ep7312" board.Wolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Marius Gröger <mag@sysgo.de>
2011-09-07Makefile : fix generation of cpu related asm-offsets.hStefano Babic
commit 0edf8b5b2fa0d210ebc4d6da0fd1aceeb7e44e47 breaks building on a different directory with the O= parameter. The patch wil fix this issue, generating always asm-offsets.h before the other targets. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Matthias Weisser <weisserm@arcor.de> CC: Wolfgang Denk <wd@denx.de>
2011-09-05Flush cache after the OS image is loaded into the memory.Diana CRACIUN
Since we are loading an executable image into memory we need flush it out of the cache to possible maintain coherence on CPUs with split instruction and data caches. We do this for other executable image loading command. On PowerPC once we do this we no longer need to explicitly flush the dcache on multi-core systems in the BOOTM_STATE_OS_PREP phase. We now treat the BOOTM_STATE_OS_PREP as a no-op to maintain backwards compatibility with the bootm subcommand. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Diana CRACIUN <Diana.Craciun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-04Merge branch 'master' of git://git.denx.de/u-boot-coldfireWolfgang Denk
* 'master' of git://git.denx.de/u-boot-coldfire: ColdFire:Clean up the CONFIG_STANDALONE_LOAD_ADDR usage ColdFire:Add mb for 5253 dram initialization ColdFire:Define the DM9000 byteswap for M5253 board. ColdFire:Update the env settings for several boards. ColdFire:disable the NFS define for 52277 board. ColdFire:Update the timer_init since it was unified. ColdFire: Cleanup for partial linking and --gc-sections ColdFire: Update compile flags for each CPUs ColdFire:Fix the configuration broken for some boards.
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