summaryrefslogtreecommitdiff
path: root/arch
AgeCommit message (Collapse)Author
2015-02-07ARM: atmel: sama5d4: add matrix1 base addr definitionBo Shen
Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-02-07ARM: atmel: spl: can not disable osc for sama5d4Bo Shen
The SAMA5D4 SoC on chip rc oscillator can not be disabled. Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-02-07ARM: atmel: spl: add saic to aic redirect functionBo Shen
Some SoC need to redirect the saic to aic to make the interrupt to work, here add a weak function to be replaced by real function. Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-02-07ARM: atmel: spl: add weak bus matrix init functionBo Shen
Some SoC need to configure the bus matrix, add an weak function to be replace by real function. Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-02-07ARM: atmel: sama5: add sfr register header fileBo Shen
The SFR (special function registers) can be shared bwteen sama5d3 and sama5d4 soc. Signed-off-by: Bo Shen <voice.shen@atmel.com> [whitespace adoptions for 80 char compliance] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-02-07ARM: atmel: sama5: add bus matrix header fileBo Shen
This matrix header file can be shared between sama5d3 and sama5d4 soc. Signed-off-by: Bo Shen <voice.shen@atmel.com> [whitespace adaptions for 80 char compliance] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-02-07ARM: atmel: clock: make it possible to configure HMX32Bo Shen
Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-02-06x86: Use tab instead of space to indent in PCIE_ECAM_BASEBin Meng
Space is used before 'default' in PCIE_ECAM_BASE in arch/x86/Kconfig so it looks misaligned. Replace the space with tab to indent. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06x86: Add SD/MMC support to quark/galileoBin Meng
Intel Galileo board has a microSD slot which is routed from Quark SoC SDIO controller. Enable SD/MMC support so that we can use an SD card. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06x86: Add SPI support to quark/galileoBin Meng
The Quark SoC contains a legacy SPI controller in the legacy bridge which is ICH7 compatible. Like Tunnel Creek and BayTrail, the BIOS control register offset in the ICH SPI driver is wrong for the Quark SoC too, unprotect_spi_flash() is added to enable the flash write. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06x86: galileo: Add GPIO supportBin Meng
Quark SoC has a legacy GPIO block in the legacy bridge (D0:F31), which is just the same one found in other x86 chipset. Since we programmed the GPIO register block base address, we should be able to enable the GPIO support on Intel Galileo board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06x86: quark: Initialize non-standard BARsBin Meng
Quark SoC has some non-standard BARs (excluding PCI standard BARs) which need be initialized with suggested values. This includes GPIO, WDT, RCBA, PCIe ECAM and some ACPI register block base addresses. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06x86: quark: Call MRC in dram_init()Bin Meng
Now that we have added Quark MRC codes, call MRC in dram_init() so that DRAM can be initialized on a Quark based board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06x86: quark: Enable the Memory Reference Code buildBin Meng
Turn on the Memory Reference code build in the quark Makefile. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06x86: quark: Add System Memory Controller supportBin Meng
The codes are actually doing the memory initialization stuff. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06x86: quark: Add utility codes needed for MRCBin Meng
Add various utility codes needed for Quark MRC. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06x86: quark: Add Memory Reference Code (MRC) main routinesBin Meng
Add the main routines for Quark Memory Reference Code (MRC). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06x86: quark: Bypass TSC calibrationBin Meng
For some unknown reason, the TSC calibration via PIT does not work on Quark. Enable bypassing TSC calibration and override TSC_FREQ_IN_MHZ to 400 per Quark datasheet in the Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06x86: Allow overriding TSC_FREQ_IN_MHZBin Meng
We should allow the value of TSC_FREQ_IN_MHZ to be overridden by the one in arch/cpu/<xxx>/Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06x86: Enable the Intel quark/galileo buildBin Meng
Make the Intel quark/galileo support avaiable in Kconfig and Makefile. With this patch, we can generate u-boot.rom for Intel galileo board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06x86: Add basic Intel Galileo board supportBin Meng
New board/intel/galileo board directory with minimum codes, plus board dts, defconfig and configuration files. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06x86: Add basic Intel Quark processor supportBin Meng
Add minimum codes to support Intel Quark SoC. DRAM initialization is not ready yet so a hardcoded gd->ram_size is assigned. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06x86: quark: Add Cache-As-RAM initializationBin Meng
Quark SoC contains an embedded 512KiB SRAM (eSRAM) that is initialized by hardware. eSRAM is the ideal place to be used for Cache-As-RAM (CAR) before system memory is available. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06x86: Define macros for pci configuration space accessBin Meng
Move PCI_REG_ADDR and PCI_REG_DATA from arch/x86/lib/pci_type1.c to arch/x86/include/asm/pci.h, also define PCI_CFG_EN so that these macros can be used for pci configuration space access. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06x86: quark: Add routines to access message bus registersBin Meng
In the Quark SoC, some chipset commands are accomplished by utilizing the internal message network within the host bridge (D0:F0). Accesses to this network are accomplished by populating the message control register (MCR), Message Control Register eXtension (MCRX) and the message data register (MDR). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06x86: Add header files for Intel Quark SoC definesBin Meng
device.h for integrated pci devices' bdf on Quark SoC and quark.h for various memory-mapped and i/o-mapped base addresses within SoC. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06x86: Add support for Intel Minnowboard MaxSimon Glass
This is a relatively low-cost x86 board in a small form factor. The main peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800 series CPU. So far only the dual core 2GB variant is supported. This uses the existing FSP support. Binary blobs are required to make this board work. The microcode update is included as a patch (all 3000 lines of it). Change-Id: I0088c47fe87cf08ae635b343d32c332269062156 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-06x86: Allow a UART to be set up before the FSP is readySimon Glass
Since the FSP is a black box it helps to have some sort of debugging available to check its inputs. If the debug UART is in use, set it up after CAR is available. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-06x86: Allow FSP Kconfig settings for all x86Simon Glass
While queensbay is the first chip with these settings, others will want to use them too. Make them common. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-06x86: Remove unnecessary casts and fix comment typosSimon Glass
Tidy up the FSP support code a little. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-06x86: mmc: Move common FSP functions into a common fileSimon Glass
Since these board functions seem to be the same for all boards which use FSP, move them into a common file. We can adjust this later if future FSPs need more flexibility. This creates a generic PCI MMC device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-06Merge git://git.denx.de/u-boot-marvellTom Rini
2015-02-06arm: mvebu: Add Serdes PHY config codeStefan Roese
This code is ported from the Marvell bin_hdr code into mainline SPL U-Boot. It needs to be executed very early so that the devices connected to the serdes PHY are configured correctly. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
2015-02-06arm: armada-xp: Add SPL support used to include the DDR training codeStefan Roese
This patch adds SPL support to the Marvell Armada-XP. With this addition the bin_hdr integration is not needed any more. The SPL will first initialize the serdes/PHY and the call the DDR setup and training code now integrated into mainline U-Boot. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
2015-02-06arm: db-mv784mp-gp: Enable SPL to include DDR training code into U-BootStefan Roese
This patch adds SPL support to the db-mv784mp-gp eval board. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
2015-02-06arm: maxbcm: Enable SPL to include DDR training code into U-BootStefan Roese
This patch adds SPL support to the maxbcm MV78460 based board. Including the fixed DDR configuratrion needed for the DDR training code. And the the serdes PHY init code. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
2015-02-06arm: armada-xp: Change built target to include the SPL binary as bin_hdrStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
2015-02-07ARM: UniPhier: leave the last element of boot_device_table emptyMasahiro Yamada
Checking if the pointer is NULL would be easier to know the tail of the boot_device_table[] array. For clarification, add the /* sentinel */ comment. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-02-07ARM: UniPhier: refactor pinmon commandMasahiro Yamada
The return value of get_boot_mode_sel() is used as the index of the boot_device_table[] array. Its type should be "int" rather than "u32". Use only the iterator "i" for the loop in do_pinmon(). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-02-07ARM: UniPhier: enable I2C input pins for PH1-sLD8Masahiro Yamada
To use I2C controllers on PH1-sLD8, the bit 10 (SCL0/SDA0) and bit 11 (SCL1/SDA1) of IECTRL register must be set. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-02-07ARM: UniPhier: do not compile unnecessary objectsMasahiro Yamada
It is true that unused functions are removed from the ELF image by the compiler's garbage collection but relying on it too much does not look nice. Currently, the build is taking more than it should. Refactor the makefiles to compile only files that are really needed. CONFIG_SOC_INIT and CONFIG_DRAM_INIT are no longer needed by the optimization. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-02-07ARM: UniPhier: remove unused checkboard() functionsMasahiro Yamada
Since commit 0365ffcc0bd6 (generic-board: show model name in board_init_f() too), checkboard() is invoked only when show_board_info() fails to get the model name from Device Tree. It never happens because UniPhier SoCs now only work with CONFIG_OF_CONTROL and all the root nodes of UniPhier device trees have the "model" property. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-02-07ARM: UniPhier: revive support card infoMasahiro Yamada
Since commit 0365ffcc0bd6 (generic-board: show model name in board_init_f() too), the support card information has not been displayed because check_support_card() is invoked only when show_board_info() fails to get the model name from Device Tree. This commit adds misc_init_f() function to call check_support_card() from there. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-02-07ARM: UniPhier: move SPL init functions to spl_board_init()Masahiro Yamada
Now init functions called from board_postclk_init() and dram_init() are only necessary for SPL. Move them to spl_board_init() for clean-up. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-02-07ARM: UniPhier: move pin_init() to board_early_init_f()Masahiro Yamada
Currently, I/O pin settings are not necessary for SPL. The board_early_init_f() seems a suitable place to call pin_init(). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-02-07ARM: UniPhier: set I2C offset length of on-board EEPROM in DTSMasahiro Yamada
The EEPROM chips on UniPhier reference daughter boards expect 2-byte offset address. Since 7132b9fd68a1 (dm: i2c: dts: Support an offset-len device tree property), I2C sub-nodes can have "u-boot,i2c-offset-len" property. It is convenient to set the default I2C offset address length in Device Tree, so that we do not have to set it on the command line. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-02-07ARM: UniPhier: move EEPROM device node into a separate DTSMasahiro Yamada
This EEPROM chip is installed on the expansion board commonly used on UniPhier platform. To avoid duplicated description, move the EEPROM node to a separate file and include it from other device tree sources. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-02-07ARM: UniPhier: remove dummy gpio.hMasahiro Yamada
This dummy header was introduced by commit 630bf80ebb34 (ARM: UniPhier: add dummy gpio.h to enable CONFIG_OF_CONTROL). Thanks to commit a08d643dbd85 (dm: Drop gpio.h header from fdtdec.c), such an ugly workaround is no longer needed. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-02-05x86: Make CAR and DRAM FSP code commonSimon Glass
For now this code seems to be the same for all FSP platforms. Make it common until we see what differences are required. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-05x86: Adjust the FSP types slightlySimon Glass
To avoid casts, find_fsp_header() should return a pointer. Add asmlinkage to two API functions which use that convention. UPD_TERMINATOR is common so move it into a common file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit (git 2.34.1) at 2025-01-01 20:13:02 +0000