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2017-12-04add support for Raspberry Pi Zero WDmitry Korunov
Signed-off-by: Dmitry Korunov <dessel.k@gmail.com>
2017-12-02omap2: set the ethaddr as well as the usbethaddr env var to ensure static MACPeter Robinson
The kernel gets the ethernet MAC from the ethaddr variable, the omap boards for devices with USB based eth adapters just set the usbethaddr which doesn't appear to get passed to the kernel. The same Raspberry Pi code sets both ethaddr and usbethaddr so lets do that so linux (tested 4.13 and 4.14) get a static rather than a random MAC address, while not regressing users of usbethaddr. Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
2017-12-02rockchip: clk: rk3128: fix DCLK_VOP_DIV_CON_MASKPhilipp Tomsich
The DCLK_VOP_DIV_CON_MASK should cover only bits 8 through 15. Fix this to remove an "integer-overflow on shifted constant" warning. Fixes: 9246d9e ("rockchip: rk3128: add clock driver") Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-12-02rockchip: clk: rk3128: fix NANDC_PLL_SEL_MASKPhilipp Tomsich
The PLL selector field for NANDC is only 2 bits wide. This fixes an 'int-overflow on shift' warning. Fixes: 9246d9e ("rockchip: rk3128: add clock driver") Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30rockchip: dts: rk3399-puma: add /config/sysreset-gpio propertyPhilipp Tomsich
On the RK3399-Q7, we want to trigger a full platform reset (so the various software stacks supported don't have to deal with the same complexities over and over again) in case that anything other than a power-on reset occurred. To do so, this defines the /config/sysreset-gpio property and has it point to a GPIO that will perform a power-on reset of the entire platform. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2017-11-30rockchip: dts: rk3399-puma: add a 'tsd, usb-port-power' stringlist for USB1Philipp Tomsich
USB1 is connected to the on-module USB 3.0 hub and power to the hub (actually it's a reset signal, modeled as a fixed regulator, that will be released) should be enabled only during the first probing of the device to avoid the hub from entering its low-power mode (where it tries to attach on a fixed interval, but we always miss the timeslot when U-Boot has the controller listening). This adds a 'tsd,usb-port-power' stringlist to enable the infrastructure in the board-specific usb_hub_reset_devices to find and control the fixed regulator associated with control of the USB hub. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
2017-11-30rockchip: rk3036: sdram: correct setting for pll integer modeKever Yang
According to rk3036 TRM, should be set to '1' for the pll integer mode, while the '0' means the frac mode. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30rockchip: rk3036: update clock driver for ddrKever Yang
After the MASK MACRO update, we need to update the driver at the same time. This is a fix to: 37943aa rockchip: rk3036: clean mask definition for cru reg Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30rockchip: rk3036: fix pll config for correct frequencyKever Yang
There is a fixed div-2 between PLL and clk_ddr/clk_ddrphy, so we need to double to pll output and then ddr can work in correct frequency. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30rockchip: rk3128: add evb-rk3128 supportKever Yang
evb-rk3128 is an evb from Rockchip based on rk3128 SoC: - 2 USB2.0 Host port; - 1 HDMI port; - 2 10/100M eth port; - 2GB ddr; - 16GB eMMC; - UART to USB debug port; Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30rockchip: rk3128: add pinctrl driverKever Yang
Add rk3128 pinctrl driver and grf/iomux structure definition. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30rockchip: rk3128: add clock driverKever Yang
Add rk3128 clock driver and cru structure definition. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30rockchip: rk3128: add soc basic supportKever Yang
RK3128 is a SoC from Rockchip with quad-core Cortex-A7 CPU and mali400 GPU. Support Nand flash, eMMC, SD card, USB 2.0 host and device, HDMI/LVDS/MIPI display. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30rockchip: rk3128: add device tree fileKever Yang
Add dts binding header for rk3128, files origin from kernel. Series-Changes: 2 - fix i2c address - add saradc and usb phy node - emmc using fifo mode for there is no dma support in rk3128 emmc - add some clock id in cru.h Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30Merge branch 'rmobile-mx' of git://git.denx.de/u-boot-shTom Rini
2017-11-30Merge git://git.denx.de/u-boot-marvellTom Rini
2017-11-30Merge git://git.denx.de/u-boot-x86Tom Rini
2017-11-30ARM: rmobile: Rework the ULCB CPLD driverMarek Vasut
Rework the ULCB CPLD driver and make it into a sysreset driver, since that is what the ULCB CPLD driver is mostly for. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30arm: mvebu: enable boot from NANDSean Nyekjaer
Check if we are booting from NAND and let the bootrom continue to load the rest of the bootloader Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk> Signed-off-by: Stefan Roese <sr@denx.de>
2017-11-30arm: mvebu: fix boot from UART when in fallback modeSean Nyekjaer
It's the first 8 bits of the bootrom error register that contain the boot error/fallback error code. Let's check that and continue to boot from UART. Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk> Signed-off-by: Stefan Roese <sr@denx.de>
2017-11-30arm: mvebu: add nand pinsSean Nyekjaer
Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk> Signed-off-by: Stefan Roese <sr@denx.de>
2017-11-30x86: lib: Implement standalone __udivdi3 etc instead of libgcc onesStefan Roese
This patch removes the inclusion of the libgcc math functions and replaces them by functions coded in C, taken from the coreboot project. This makes U-Boot building more independent from the toolchain installed / available on the build system. The code taken from coreboot is authored from Vadim Bendebury <vbendeb@chromium.org> on 2014-11-28 and committed with commit ID e63990ef [libpayload: provide basic 64bit division implementation] (coreboot git repository located here [1]). I modified the code so that its checkpatch clean without any functional changes. [1] git://github.com/coreboot/coreboot.git Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2017-11-30Revert "x86: bootm: Fix FIT image booting on x86"Anatolij Gustschin
This reverts commit 13c531e52a09b4e6ffa8b5a1457199b0a574cb27. The error message with FIT style image mentioned in the above commit only happens when booting using FIT image containing bzImage kernel and without setup node (setup.bin). The current documentation for x86 FIT support in doc/uImage.FIT/x86-fit-boot.txt mentions that kernel's setup.bin file is required for building x86 FIT images. The above commit breaks FIT images generated as described in the documentation. Revert it to allow booting with images built in the documented way. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2017-11-30x86: don't compare pointers to 0Heinrich Schuchardt
x86_vendor_name is defined as static const char *const x86_vendor_name[] So its elements should not be compared to 0. Remove superfluous paranthesis. Problem identified with Coccinelle. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-11-30x86: qemu: Move Cache-As-RAM memory from area mapped to ROMAnton Gerasimov
ROM has been made read-only in qemu recently (namely commit 208fa0e4: "pc: make 'pc.rom' readonly when machine has PCI enabled"). So this patch restores compatibility between U-Boot and qemu. Signed-off-by: Anton Gerasimov <anton@advancedtelematic.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: mention qemu commit title in the commit message] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-11-29board: laird: add WB50N CPU moduleBen Whitten
This board is based on the Atmel sama5d3 eval boards. Supporting the following features: - Boot from NAND Flash - Ethernet - FIT - SPL Signed-off-by: Ben Whitten <ben.whitten@lairdtech.com> Signed-off-by: Dan Kephart <dan.kephart@lairdtech.com>
2017-11-29board: laird: add WB45N CPU moduleBen Whitten
This board is based on the Atmel 9x5 eval board. Supporting the following features: - Boot from NAND Flash - Ethernet - FIT - SPL Signed-off-by: Ben Whitten <ben.whitten@lairdtech.com> Signed-off-by: Dan Kephart <dan.kephart@lairdtech.com>
2017-11-29ARM: dts: Rename logicpd-toredp-37xx-devkit in U-BootAdam Ford
In U-Boot, this device tree is compatible with both the Torpedo and SOM-LV kits. Let's rename it in the device tree since the U-Boot code and show a more generic OMAP3 name. The code auto detects between the two and loads the proper DTB file for Linux. This would eliminate the SOM-LV showing the name Torpedo during boot and hopefully eliminate some confusion. Signed-off-by: Adam Ford <aford173@gmail.com>
2017-11-29board: atmel: add sama5d2_ptc_ek boardLudovic Desroches
Add the SAMA5D2 PTC EK board and remove the SAMA5D2 PTC ENGI board which was a prototype. Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-11-29ARM: at91: add sama5d2 smc headerLudovic Desroches
Add a header for SAMA5D2 SMC since it's not compatible with SAMA5D3 one. Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com> [wenyou: fix the wrong base address of the SMC register] Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-11-29mach-stm32: Factorize MPU's region config for STM32 SoCsPatrice Chotard
MPU's region setup can be factorized between STM32F4/F7/H7 SoCs family and used a common MPU's region config. Only one exception for STM32H7 which doesn't have device area located at 0xA000 0000. For STM32F4, configure_clocks() need to be moved from arch_cpu_init() to board_early_init_f(). Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-29stm32: migrate clock structs in include/stm32_rcc.hPatrice Chotard
In order to factorize code between STM32F4 and STM32F7 migrate all structs related to RCC clocks in include/stm32_rcc.h Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-29clk: clk_stm32fx: add clock configuration for mmc usagePatrice Chotard
MMC block needs 48Mhz source clock, for that we choose to select the SAI PLL. Update also stm32_clock_get_rate() to retrieve the MMC clock source needed in MMC driver. STM32F4 uses a different RCC variant than STM32F7. For STM32F4 sdmmc clocks bit are located into dckcfgr register whereas there are located into dckcfgr2 registers on STM32F7. In both registers, bits CK48MSEL and SDMMC1SEL are located at the same position. Signed-off-by: Christophe Priouzeau <christophe.priouzeau@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-29clk: stm32fx: migrate define from rcc.h to driverPatrice Chotard
STM32F4 doesn't get rcc.h file, to avoid compilation issue, migrate RCC related defines from rcc.h to driver file and remove rcc.h file. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-29ARM: DTS: stm32: update rcc compatible for STM32F746Patrice Chotard
Align the RCC compatible string with the one used by kernel. It will allow to use the same clock driver for STM32F4 and STM32F7 and to manage the differences between the 2 SoCs Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-29clk: stm32f7: retrieve PWR base address from DTPatrice Chotard
PWR IP is used to enable over-drive feature in order to reach a higher frequency. Get its base address from DT instead of hard-coded value Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-29ARM: DTS: stm32: add pwrcfg node for stm32f746Patrice Chotard
This node is needed to enable performance mode when system frequency is set up to 200Mhz. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-30nds32: dts: Support ftsdc010 DM.Rick Chen
Add dts to support ftsdc010 dm flow on AG101P/AE3XX platform. Signed-off-by: Rick Chen <rick@andestech.com>
2017-11-30ARM: rmobile: Migrate boards to RCar IIC driversMarek Vasut
Stop using the old ad-hoc SH I2C driver and use the new RCar IIC driver instead. The SH I2C driver should be deprecated and removed eventually. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30ARM: rmobile: Use PRR driver on all Gen3 boardsMarek Vasut
Mark the PRR as u-boot,dm-pre-reloc in all Gen3 board DTs as it is needed very early and turn on the CONFIG_SYSCON to allow the PRR driver to bind as a syscon uclass. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30ARM: rmobile: Convert PRR to DM and OF controlMarek Vasut
Implement DM driver for the Renesas PRR into RCar cpu info and convert all users with DM and OF enabled to this new driver. This means all of the boards with DM and OF enabled can fetch PRR address from DT, which is useful on ie. V3M which has different PRR address than the rest of Gen3 SoCs. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30ARM: rmobile: Zap checkboard on Gen3Marek Vasut
The checkboard() function showing hard-coded board model for which the U-Boot was built is superseded on Gen3 by show_board_info() displaying the Model from device tree. Add small ifdef to stop compiling the function into U-Boot. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30ARM: rmobile: Unify R8A7795 and R8A7796 in rmobile MakefileMarek Vasut
Since both R8A7795 and R8A7796 now use the same files, unify the Makefile entry to CONFIG_RCAR_GEN3. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30ARM: rmobile: Unify memory map for RCar Gen3Marek Vasut
Unify the R7A7795 and R8A7796 memory maps in memmap-gen3 and, for now, select which one is used based on which SoC is selected. Since this is done in C code instead of statically assigned now, the decision can be taken by PRR SoC match as well, which will be done in a subsequent patch. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30ARM: rmobile: Add PRR CPU ID macrosMarek Vasut
Replace the ad-hoc values in the PRR CPU ID table with macros, so that users can use rmobile_get_cpu_type() can compare the returned value with these macros to figure out on which CPU they are running. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30ARM: rmobile: Dispose of r8a779x.h for Gen3Marek Vasut
These files no longer contain anything useful, so remove them. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30ARM: rmobile: Zap Gen3 PFC tablesMarek Vasut
These old PFC tables are no longer needed as there is now a proper PFC pinmux driver in drivers/pinctrl/renesas . Remove them . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30ARM: rmobile: Drop SDHI address macros from Gen3Marek Vasut
Since the RCar Gen3 no longer uses the SH SDHI driver, but rather uses the Matsushita SD driver, which loads all the properties from device tree, these macros are no longer used, remove them. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30ARM: rmobile: Fix eMMC signal voltage on ULCBMarek Vasut
The eMMC is 1V8 device only and the signaling is always 1V8, fix the DT for ULCB to describe the hardware correctly. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-29Merge tag 'xilinx-for-v2018.01' of git://www.denx.de/git/u-boot-microblazeTom Rini
Xilinx changes for v2018.1 Zynq: - Add support for Syzygy and cc108 boards - Add support for mini u-boot configurations (cse) - dts updates - config/defconfig updates in connection to Kconfig changes - Fix psu_init handling ZynqMP: - SPL fixes - Remove slcr.c - Fixing r5 startup sequence - Add support for external pmufw - Add support for new ZynqMP chips - dts updates - Add support for zcu102 rev1.0 board Drivers: - nand: Support external timing setting and board init - ahci: Fix wording - axi_emac: Wait for bit, non processor mode, readl/write conversion - zynq_gem: Fix SGMII/PCS support
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