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2018-08-06mvebu: support UART boot imageBaruch Siach
The kwboot utility can use the generated image to boot mvebu SoCs from UART. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
2018-08-06mvebu: select boot device at SoC levelBaruch Siach
Move the gdsys Controlcenter DC specific build time kwbimage.cfg generation code into the mach-mvebu/ directory to be shared by all 32bit mvebu platforms. Remove board specific kwbimage.cfg files, and use the generated one instead. These files are all identical, with two exceptions. Clearfog and Helios4 use the sdio boot device, whereas all others use spi. Update the defconfigs for the exceptional boards to generate the same kwbimage.cfg as before. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
2018-08-06mvebu: consolidate SPL boot device config symbolsBaruch Siach
Use MVEBU_SPL_BOOT_DEVICE_* to select between SPI and MMC, instead of board specific symbols. This commit enables the boot device selection menu to all mvebu platforms, but it is only effective on Turris Omnia and gdsys Controlcenter DC platforms. A following commit will enable boot selection for other platforms. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
2018-08-06mvebu: a38x: drop duplicate platform id symbolsBaruch Siach
Use generic mvebu Kconfig symbols like all other mvebu boards. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
2018-08-06arm64: zynqmp: Add support for Avnet Ultra96Michal Simek
Avnet Ultra96 is rebranded Xilinx zcu100 revC/D. Add new defconfig files and point to origin internal board name. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-06arm: zynq: add support for the zybo z7 boardLuis Araneda
The board is manufactured by Digilent Main features: - Soc: XC7Z010 (Z7-10) or XC7Z020 (Z7-20) - RAM: 1 GB DDR3L - FLASH: 16 MB QSPI - 1 Gbps Ethernet - USB 2.0 - microSD slot - Pcam camera connector - HDMI Tx and Rx - Audio codec: stereo out, stereo in, mic - 5 (Z7-10) or 6 (Z7-20) Pmod ports - 6 push-buttons, 4 switches, 5 LEDs - 1 (Z7-10) or 2 (Z7-20) RGB LEDs Signed-off-by: Luis Araneda <luaraneda@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-06Kconfig: Move config SYS_MALLOC_LEN to Kconfig for zynqSiva Durga Prasad Paladugu
This patch moves the the config SYS_MALLOC_LEN to Kconfig. It will be just for Zynq arch and to do will be for all other archs. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-06arm: zynq: Fix indentation for zynq-cse targetsMichal Simek
Trivial DT style fixes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-06arm: zynq: Remove fclk-enable property for cse-nor targetMichal Simek
Mini cse NOR configuration is running without PL that's why there is no reason to enable clock to PL. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-06arm: zynqmp: Fix sdhci clock in emmc1 mini configurationMichal Simek
Add missing clocks property with fix clock-names property to be aligned with emmc0 configuration and binding doc. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-06arm: spring: fix alias of mmc correctlyMinkyu Kang
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2018-08-06arm: exynos5: fix warning of dtsMinkyu Kang
remove this warning: avoid_unnecessary_addr_size Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2018-08-06arm: exynos4: fix warning of dtsMinkyu Kang
remove this warning: avoid_unnecessary_addr_size Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2018-08-04Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini
2018-08-03ARM: dts: stm32: remove cd-inverted for stm32429i-evalPatrice Chotard
As cd-inverted property is no more used by arm_pl180_mmci driver, remove it. Update cd-gpios active level accordingly. Reported-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-08-03armv8: make SPL exception vectors optionalAndre Przywara
Even though the exception vector table is a fundamental part of the ARM architecture, U-Boot mostly does not make real use of it, except when crash dumping. But having it in takes up quite some space, partly due to the architectural alignment requirement of 2KB. Since we don't take special care of that, the compiler adds a more or less random amount of padding space, which increases the image size quite a bit, especially for the SPL. On a typical Allwinner build this is around 1.5KB of padding, plus 1KB for the vector table (mostly padding space again), then some extra code to do the actual handling. This amounts to almost 10% of the maximum image size, which is quite a lot for a pure debugging feature. Add a Kconfig symbol to allow the exception vector table to be left out of the build for the SPL. For now this is "default y" for everyone, but specific defconfigs, platforms or .config files can opt out here at will, to mitigate the code size pressure we see for some SPLs. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-08-03armv8: Reduce exception handling codeAndre Przywara
The arm64 exception handling code is quite big, mostly due to architectural alignment requirements. Each exception entry spans 32 instructions, which sounds generous, but is too small to fit all of the save/branch/restore code in there. So at the moment we use only four instructions, branching into shared save and restore routines. To not leave the space for those remaining 28 instructions wasted, let's split the save and restore routines and stuff them into the gaps. This saves about 250 bytes of code, which is helpful for those tight SPLs. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-08-03clk: add clk_valid()Fabrice Gasnier
Add clk_valid() to check for optional clocks are valid. Call clk_valid() in test/dm/clk.c and add relevant test routine to sandbox clk tests. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-03Merge git://git.denx.de/u-boot-dmTom Rini
2018-08-01ARM: tegra: align carveout sizeStephen Warren
Align the size of the carveout region to 2M. This ensures that the size can be accurately represented by an LPAE page table that uses sections. This solves a bug (hang at boot time soon after printing the DRAM size) that only shows up when the following two commits are merged together: d32e86bde8a3 ARM: HYP/non-sec: enable ARMV7_LPAE if HYP mode is supported 6e584e633d10 ARM: tegra: avoid using secure carveout RAM Cc: Mark Kettenis <kettenis@openbsd.org> Cc: Alexander Graf <agraf@suse.de> Acked-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2018-08-01binman: Rename 'position' to 'offset'Simon Glass
After some thought, I believe there is an unfortunate naming flaw in binman. Entries have a position and size, but now that we support hierarchical sections it is unclear whether a position should be an absolute position within the image, or a relative position within its parent section. At present 'position' actually means the relative position. This indicates a need for an 'image position' for code that wants to find the location of an entry without having to do calculations back through parents to discover this image position. A better name for the current 'position' or 'pos' is 'offset'. It is not always an absolute position, but it is always an offset from its parent offset. It is unfortunate to rename this concept now, 18 months after binman was introduced. However I believe it is the right thing to do. The impact is mostly limited to binman itself and a few changes to in-tree users to binman: tegra sunxi x86 The change makes old binman definitions (e.g. downstream or out-of-tree) incompatible if they use the 'pos = <...>' property. Later work will adjust binman to generate an error when it is used. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-08-01Merge tag 'arc-updates-for-2018.09-rc2' of git://git.denx.de/u-boot-arcTom Rini
That's a set of prety minor changes and fixes for ARC. Among them: * Improvement in CREG GPIO driver used on ARC dev boards that allow us to re-use the driver for SPI's chip select * Enable SPI-flsh on AXS10x boards which allows to update U-Boot binary that gets loaded by boot-ROM * Fix accommodating always utilized unaligned access by GCC for ARC starting from 8.1.0
2018-07-31dm: Fix CMD_DM enablingMichal Simek
The patch "dm: Change CMD_DM enabling" (sha1: 08a00cba06a7e608ae65e3d7ea225cf8c639429d) was incorrectly updated and PICO_IMX7D is missing imply CMD_DM and WARP7 has it twice. This patch is fixing it. Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-31board: sun50i: h6: Add OrangePi One Plus initial supportJagan Teki
OrangePi One Plus is Allwinner H6 based open-source SBC, which support: - Allwinner H6 Quad-core 64-bit ARM Cortex-A53 - GPU Mali-T720 - 1GB LPDDR3 RAM - AXP805 PMIC - 1Gbps GMAC via RTL8211 - USB 2.0 Host, OTG - HDMI port - 5V/2A DC power supply Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-07-31sunxi: add support for Pine H64 boardIcenowy Zheng
Pine H64 is a SBC with Allwinner H6 SoC produced by Pine64. It features 1GiB/2GiB/4GiB(3GiB usable) DRAM, two USB 2.0 ports, one USB 3.0 port and a mPCIE slot. Add support for it. The device tree is from Linux next-20180720. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31sunxi: add support for Allwinner H6 SoCIcenowy Zheng
Allwinner H6 is a new SoC from Allwinner features USB3 and PCIe interfaces. This patch adds support for it. The corresponding DTSI file, from Linux next-20180720, is also introduced. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31sunxi: add DRAM support to H6Icenowy Zheng
The Allwinner H6 SoC comes with a set of new DRAM controller+PHY combo. Both the controller and the PHY seem to be originate from DesignWare, and are similar to the ones in ZynqMP SoCs. This commit introduces an initial DRAM driver for H6, which contains only LPDDR3 support. The currently known SBCs with H6 all come with LPDDR3 memory, including Pine H64 and several Orange Pi's. The BSP DRAM initialization code is closed source and violates GPL. Code in this commit is written by experimenting, referring the code/document of other users of the IPs (mainly the ZynqMP, as it's the only found PHY reference) and disassebling the BSP blob. Thanks for Jernej Skrabec for review and fix some issues in this driver (including the most critical one which made it to work), and rewrite some code from register dump! Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31sunxi: add MMC support for H6Icenowy Zheng
The Allwinner H6 SoC has 3 MMC controllers like the ones in A64, with the MMC2 come with the capability to do crypto by EMCE. Add MMC support for H6. EMCE support is not added yet. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31sunxi: add UART0 setup for H6Icenowy Zheng
The UART0 on H6 is available at PH bank (and PF bank, but the PF one is muxed with SD card). Add pinmux configuration. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31sunxi: use sun6i-style watchdog for H6Icenowy Zheng
The H6 SoC has a sun6i-style watchdog in its timer part. Enable the usage of it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31sunxi: add clock code for H6Icenowy Zheng
The new Allwinner H6 SoC has a brand new CCU layout. Add clock code for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31sunxi: change RMR64's RVBAR address for H6Icenowy Zheng
Allwinner H6 has a different RVBAR address with A64/H5. Add conditional RVBAR configuration into the code which does RMR switch. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31sunxi: add basic memory map definitions of H6 SoCIcenowy Zheng
The Allwinner H6 SoC come with a totally new memory map. Add basical definition of the new memory map into a header file, and let the cpu.h header include it in the situation of H6. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31sunxi: change SUNXI_HIGH_SRAM option to SUNXI_SRAM_ADDRESSIcenowy Zheng
The new Allwinner H6 SoC has its SRAM A1 at neither 0x0 nor 0x10000, but it's at 0x20000. Thus the SUNXI_HIGH_SRAM option needs to be refactored to support this new configuration. Change it to SUNXI_SRAM_ADDRESS, which holds the real address of SRAM A1 in the memory map. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31ARC: Enable unaligned access in hardware if compiler uses itAlexey Brodkin
Even if ARC core might handle unaligned access to data this hardware feature by default is disabled. But GCC starting from 8.1.0 unconditionally uses it for ARC HS cores. Which leads to quite strange and fatal run-time failures like the one below if HW is not configured properly: | hsdk# sf probe | Misaligned data access exception @ 0xbff794d4 | ECR: 0x000d0000 | RET: 0xbff794d4 | BLINK: 0xbff79644 | STAT32: 0x00000800 | GP: 0x1003e000 r25: 0xbfd58f08 | BTA: 0xbff794a4 SP: 0xbfd58cd4 FP: 0xbfd58ef0 | LPS: 0xbff90240 LPE: 0xbff90244 LPC: 0x00000000 | r00: 0x00000000 r01: 0x00000003 r02: 0x000026bf | r03: 0x00000000 r04: 0x00000100 r05: 0x00000000 | r06: 0x00000001 r07: 0x00000000 r08: 0x1dcd6500 | r09: 0x00000000 r10: 0x00200000 r11: 0x00000000 | r12: 0x1b3d4440 r13: 0xbff9eca4 r14: 0xbfd59d68 | r15: 0xbfd60cd0 r16: 0x00000000 r17: 0x00000000 | r18: 0xbff9ed14 r19: 0xbfd59c78 r20: 0xbfd58d40 | r21: 0xbfd58d44 r22: 0x00000000 r23: 0x00000000 | r24: 0xbfd59ba8 | Resetting CPU ... Now we're checking for __ARC_UNALIGNED__ define emitted by the compiler if it's going to use unaligned access and then we force-enable it in hardware too. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-07-31AXS10x: add spi flash supportEugeniy Paltsev
AXS10x boards have n25q512 spi flash IC, so add corresponding nodes to device tree and enaple corresponding options in defconfig. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-07-31GPIO: CREG: improve flexibility of hsdk-creg-gpio driverEugeniy Paltsev
CREG GPIO is a driver for weird soc-specific output ports, which are controlled by some fields in memory mapped register. Example: 31 9 7 5 0 < bit number | | | | | [ not used | gpio-1 | gpio-0 | <-shift-> ] < 32 bit register ^ ^ | | write 0x2 == set output to "1" (activate) write 0x3 == set output to "0" (deactivate) As of tooday we only support fixed (hardcoded) bit per gpio line, activate / deactivatei and shift values. Fix that by read them from device tree to be able to use this driver for other boards. Remove "hsdk" prefix from compatible string as this driver can be used with different boards like HSDK, AXS101, AXS103, etc. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-07-30Merge tag 'signed-efi-next' of git://github.com/agraf/u-bootTom Rini
Patch queue for efi - 2018-07-25 Highlights this time: - Many small fixes to improve spec compatibility (found by SCT) - Almost enough to run with sandbox target - GetTime() improvements - Enable EFI_LOADER and HYP entry on ARMv7 with NONSEC=y
2018-07-30Kconfig: Sort bool, default, select and imply optionsMichal Simek
Another round of sorting Kconfig entries aplhabetically. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-30dm: Change CMD_DM enablingMichal Simek
CMD_DM is used for debug purpose and it shouldn't be enabled by default via Kconfig. Unfortunately this is in the tree for quite a long time that's why solution is to use imply DM for all targets which are enabling DM. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-30Kconfig: Sort bool, default, select and imply optionsMichal Simek
Fix Kconfig bool, default, select and imply options to be alphabetically sorted. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-07-30Kconfig: Replace spaces with tabs and missing newlineMichal Simek
Trivial Kconfig cleanup. Use tabs instead of spaces and every Kconfig entry should be separated by newline. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-27Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
2018-07-26Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini
2018-07-26tegra: beaver/apalis: Fix DTC warningTom Warren
Fix warning when compiling tegra30-beaver/-apalis.dts with latest DTC: "Warning (avoid_unnecessary_addr_size): /pci/pch@1f,0: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property" Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-07-26ARM: tegra: avoid using secure carveout RAMStephen Warren
If a secure carveout exists, U-Boot cannot use that memory. Fix carveout_size() to reflect this, and hence transitively fix usable_ram_size_below_4g() and board_get_usable_ram_top(). This change ensures that when U-Boot copies the secure monitor code to install it, the copy target is not in-use for U-Boot code/data. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-07-26ARM: PSCI: Enable the PSCI nodeStephen Warren
When fixing up the DT to report PSCI support, explicitly enable the node. DTs may ship with the node disabled in case a PSCI implementation is not present, and expect any PSCI implementation to enable the node if they are actually present. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-07-26ARM: PSCI: Support PSCI v0.2Stephen Warren
Enhance the PSCI DT editing code to allow setting a PSCI v0.2 compatible value in the DT. The CONFIG_ option is added to the whitelist to match the existing PSCI_1_0 option. While not adding new options to Kconfig isn't ideal, I figure it's better to keep related options together. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-07-26ARM: define MON_MODEStephen Warren
Add a MON_MODE define for ARM's monitor mode. This can be used later by a secure monitor to avoid hard-coding mode IDs. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-07-26ARM: tegra: implement RAM repairBibek Basu
RAM repair has a few pre-requisites: 1) PMIC power supply (rail) enabled. 2) PMC CRAIL power partition powered. 3) Fuse clock active (it's the default). 4) PLLP reshift branch enabled (it's the default, when PLLP is active). RAM repair also only need run whenever specific partitions are powered (main SoC and CCPLEX respectively); RAM repair does not need to be triggered when any other partition changes state. start_cpu() needs to be re-ordered slightly to match these requirements. Note that C0NC and CE0 aren't required for RAM repair to operate, but they also do no harm, so the entire of powerup_cpus() is moved rather than splitting it up. The call to remove_cpu_resets() is moved last to ensure that all other actions complete before releasing reset; since the PMC power partitions are now enabled early, releasing reset is what causes the CPUs to start executing code, and RAM repair must complete before the CPU boots. Note that this commit is the result of squashing a numbmer of commits in NVIDIA's downstream L4T branch, hence the multiple signoffs below. Signed-off-by: Bibek Basu <bbasu@nvidia.com> Signed-off-by: Sandipan Patra <spatra@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
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