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2020-07-11ARM: uniphier: remove sbc/ directoryMasahiro Yamada
Now that this directory contains only uniphier_sbc_boot_is_swapped(), move it to boot-device.c and delete the sbc/ directory entirely. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11bus: uniphier-system-bus: move hardware init from board filesMasahiro Yamada
Move the bus initialization code to this driver from board files. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11bus: uniphier-system-bus: add UniPhier System Bus driverMasahiro Yamada
Since commit 1517126fdac2 ("ARM: uniphier: select DM_ETH"), DM-based drivers/net/smc911x.c is compiled, but it is never probed because the parent node lacks the DM-based driver. I need a skeleton driver to populate child devices (but the next commit will move more hardware settings to the this driver). I put this to drivers/bus/uniphier-system-bus.c because this is the same path as the driver in Linux kernel. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11ARM: uniphier: remove support for NOR Flash on support cardMasahiro Yamada
I actually do not see this used these days because eMMC or NAND is used for non-volatile devices. Dump the burden to maintain this crappy code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11ARM: uniphier: remove unused uniphier_sbc_init_admulti()Masahiro Yamada
This was used by the old sLD3 SoC, the support of which was removed by commit 00aa453ebf56 ("ARM: uniphier: remove sLD3 SoC support"). There is no more user of this function. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11ARM: uniphier: fix build error when CONFIG_MICRO_SUPPORT_CARD=nMasahiro Yamada
If CONFIG_MICRO_SUPPORT_CARD is unset, the build fails due to function redefinition. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11ARM: uniphier: sync with Linux 5.8-rc4Masahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11ARM: uniphier: consolidate SoC select menuMasahiro Yamada
Currently, the supports for the following two ARMv7 SoC groups are exclusive, because the boot ROM loads the SPL to a different address: - LD4, sLD8 (SPL is loaded at 0x00040000) - Pro4, Pro5, PXs2, LD6b (SPL is loaded at 0x00100000) This limitation exists only when CONFIG_SPL=y. Instead of using crappy CONFIG options, checking SPL and SPL_TEXT_BASE is cleaner. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11Revert "ARM: uniphier: add weird workaround code for LD20"Masahiro Yamada
This reverts commit 45f41c134baf5ff1bbf59d33027f6c79884fa4d9. This weird workaround was the best I came up with at that time to boot U-Boot from TF-A. I noticed U-Boot successfully boots on LD20 (i.e. CA72 CPU) by using the latest TF-A. Specifically, since the following TF-A commit, U-Boot runs at EL2 instead of EL1, and this issue went away as a side-effect. |commit f998a052fd94ea082833109f25b94ed5bfa24e8b |Author: Masahiro Yamada <yamada.masahiro@socionext.com> |Date: Thu Jul 25 10:57:38 2019 +0900 | | uniphier: run BL33 at EL2 | | All the SoCs in 64-bit UniPhier SoC family support EL2. | | Just hard-code MODE_EL2 instead of using el_implemented() helper. | | Change-Id: I7ab48002c5205bc8c013e1b46313b57d6c431db0 | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> However, if I reverted that, this problem would come back, presumably because some EL1 code in U-Boot triggers this issue. Now that commit f8ddd8cbb513 ("arm64: issue ISB after updating system registers") fixed this issue properly, this weird workaround is no longer needed irrespective of the exception level at which U-Boot runs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-10Merge tag 'rpi-next-2020.10' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-raspberrypi - add support for PCI and XHCI for RPi4 (64 bit only) - optionally reset XHCI device on registration - enable USB_KEYBOARD for rpi_4_defconfig
2020-07-10rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit)Marek Szyprowski
Create a non-cacheable mapping for the 0x600000000 physical memory region, where MMIO registers for the PCIe XHCI controller are instantiated by the PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM 32bit mode, this region is mapped at 0xff800000 CPU virtual address. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
2020-07-10arm: provide a function for boards init code to modify MMU virtual-physical mapMarek Szyprowski
Provide function for setting arbitrary virtual-physical MMU mapping and cache settings for the given region. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2020-07-10arm: update comments to the common styleMarek Szyprowski
Update the comments in include/asm/system.h to the common style. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2020-07-10arm: rpi: Add function to trigger VL805's firmware loadNicolas Saenz Julienne
On the Raspberry Pi 4, after a PCI reset, VL805's (a xHCI chip) firmware may either be loaded directly from an EEPROM or, if not present, by the SoC's VideCore (the SoC's co-processor). Introduce the function that informs VideCore that VL805 may need its firmware loaded. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-07-09Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86Tom Rini
- Add two- and three-argument versions of CONFIG_IS_ENABLED in linux/kconfig.h - Adds a new feature which supports copying modified parts of the frame buffer to the uncached hardware buffer - Enable the copy framebuffer on various x86 targets
2020-07-09rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 64bit)Marek Szyprowski
Create a non-cacheable mapping for the 0x600000000 physical memory region, where MMIO registers for the PCIe XHCI controller are instantiated by the PCIe bridge. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-07-09rpi4: shorten a mapping for the DRAMMarek Szyprowski
Remove the overlap between DRAM and device's IO area. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-07-09Merge tag 'for-v2020.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2cTom Rini
i2c changes for v2020.10 - Add support for I2C controllers found on Octeon II/III and Octeon TX TX2 SoC platforms. - Add I2C controller support for Cortina Access CAxxxx SoCs - new rtc methods, rtc command, and tests - imx_lpi2c: Improve the codes to use private data - stm32f7_i2c.c: Add new compatible "st,stm32mp15-i2c" - stm32f7_i2c.c: Add Fast Mode Plus support - pwm: Add PWM driver for SiFive SoC
2020-07-09arm: kirkwood: add DT spi0 alias to LaCie boardsSimon Guinot
The spi0 alias is needed by the environment code to retrieve the SPI flash. This patch adds some -u-boot.dtsi files, providing the spi0 aliases, for all the following Kirkwood-based LaCie boards: - d2 Network v2 - Internet Space v2 - 2Big Network v2 - Network Space v2 - Network Space Lite v2 - Network Space Max v2 - Network Space Mini v2 Note that this -u-boot.dtsi files will be removed as soon as the spi0 aliases will be available in the upstream Linux dtsi files. Signed-off-by: Simon Guinot <simon.guinot@sequanux.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-07-09arm: mvebu: helios4: sync helios4 config to clearfog and dts to kernelDennis Gilmore
The helios4 is built on the same microsom as the clearfog, by syncing the config we enable the same featureset that exists in the som on the helios4. The current config does not boot as some of the clearfog changes needed to be made on the helios4 also, generally speaking most changes for the clearfog should also be made on the helios4. Signed-off-by: Dennis Gilmore <dennis@ausil.us> Reviewed-by: Stefan Roese <sr@denx.de>
2020-07-09arm: mvebu: a38x: Adjust UTMI PHY parametersChris Packham
When running USB compliance tests on our Armada-385 hardware platforms we have seen some eye mask violations. Marvell's internal documentation says: Based on silicon test results, it is recommended to change the impedance calibration threshold setting to 0x6 prior to calibration. Port changes from Marvell's u-boot fork[1] to address this. [1] - https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/a6221551 Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2020-07-09arm: mvebu: a38x: Fix typoChris Packham
Fix spelling of Alignment. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2020-07-09x86: apl: Re-enable loading of SPLSimon Glass
At present the SPL loader is not included in the TPL image so SPL cannot be loaded. Fix it by including this file for both SPL and TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Fixes: c87f9ce2273 ("x86: Don't build some unused objects in TPL") Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-09arm: cmd_stm32prog: Fix the CONFIG_IS_ENABLED() usageBin Meng
Add parentheses around CONFIG_IS_ENABLED() in the if statement, to fix potential build failures. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-07-09x86: fsp: video: Allocate a frame buffer when neededSimon Glass
When the copy framebuffer is in use, we must also have the standard U-Boot framebuffer available. Update the FSP driver to support this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-09x86: fsp: Reinit the FPU after FSP meminitSimon Glass
The APL FSP appears to leave the FPU in a bad state in that it has registers in use. This causes an error when the next FPU operation is performed. Work around this by re-resetting the FPU after calling FSP-M. This allows the freetype console to work correctly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-09test: dm: rtc: add test of dm_rtc_read, dm_rtc_writeRasmus Villemoes
Define a few aux registers and check that they can be read/written individually. Also check that one can access the time-keeping registers directly and get the expected results. Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-07-08Merge tag 'u-boot-amlogic-20200708' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - Add proper Odroid-N2 board support code - Add support for Odroid-C4 single board computer
2020-07-08ARM: dts: meson-sm1-odroid-c4: add ethernet PHY resetNeil Armstrong
The PHY needs a reset in order to be functionnal for U-Boot, add the old PHY reset bindings for dwmac until we support the new bindings in the PHY node. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Anand Moon <linux.amoon@gmail.com>
2020-07-08boards: amlogic: add Odroid C4 supportChristian Hewitt
Odroid C4 is an Amlogic SM1 device, the board config and board documentation are adapted from the Odroid-N2 support from the same vendor. Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> [narmstrong: fix odroid-c4.rst typos and structure] Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Anand Moon <linux.amoon@gmail.com>
2020-07-08ARM: dts: sync amlogic G12A/G12B/SM1 DT from Linux 5.8-rc1Christian Hewitt
This imports the changes and the new Odroid-C4 board from the Linux commit b3a9e3b9622a ("Linux 5.8-rc1"). Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Anand Moon <linux.amoon@gmail.com>
2020-07-07Merge tag 'u-boot-rockchip-20200708' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - dts sync from kernel for rk3399 boards; - Add Radxa Rock Pi N8, N10; - Some feature update for Pinebook Pro;
2020-07-07arm: juno: Enable DM_ETHAndre Przywara
The smc911X driver is now DM enabled, so we can switch the Juno board over to use DM_ETH for the on-board Fast Ethernet device. Works out of the box by using the DT. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2020-07-07arm: use correct argument size of special registersHeinrich Schuchardt
Compiling with clang on ARMv8 shows errors like: ./arch/arm/include/asm/system.h:162:32: note: use constraint modifier "w" asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc"); ^~ %w0 These errors are due to using an incorrect size for the variables used for writing to and reading from special registers which have 64 bits on ARMv8. Mask off reserved bits when reading the exception level. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-07-07arm: remove outdated comment concerning -ffixed-x18Heinrich Schuchardt
Clang 9 supports -ffixed-x18. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-07owl: Kconfig: Enable DM eth for OWL platformAmit Singh Tomar
This patch selects CONFIG_DM_ETH (ethernet driver is base on DM model) for Action semi owl SoC. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2020-07-07arm: dts: s700: add node for ethernet controllerAmit Singh Tomar
This patch adds node for ethernet controller found on Action Semi OWL S700 SoC. Since, there is no upstream Linux binding exist for S700 ethernet controller, Changes are put in u-boot specific dtsi file. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2020-07-07net: designware: s700: Add glue code for S700 macAmit Singh Tomar
This patchs adds glue logic to enable designware mac present on Action Semi based S700 SoC, Configures SoC specific bits. Undocumented bit that programs the PHY interface select register comes from vendor source. It has been tested on Cubieboard7-lite based on S700 SoC. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2020-07-07clk: actions: Add Ethernet clocksAmit Singh Tomar
This commit adds clocks needed for ethernet operations for Actions OWL family of SoCs (S700 and S900). Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2020-07-07Actions: OWL: Calculate SDRAM sizeAmit Singh Tomar
Calculate the SDRAM size from DDR capacity register registers instead of using hard-coded value. This is quite useful to get correct size on differnt boards based on Actions OWL family of SoCs (S700 and S900). There is no documentation available that talks about DDR registers, and this is very much taken from vendor source. This commit lets Linux boot on Cubieboard7-lite(based on S700). Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2020-07-07Merge tag 'u-boot-stm32-20200707' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - arch and board update for stm32mp15: - use OPP information in device tree for 800MHz/650MHz support - ram: inprovments of test command - solve boot on closed chip when access to DBGMCU_IDC is protected - stm32prog command: Add "device anme" during USB enumeration - update configs: activate WATCHDOG and 'env erase' command, increase teed partition, support SD card after NOR boot by default and use env info in env_check - some sboard cleanups: gpio hog in dh board, specific driver for type-c stusb1600 controller code in a driver move part of code in spl.c and in common directory - fix STM32 compatible for dwc_eth_qos driver - support of new pinctrl ops get_dir_flags/set_dir_flags in stm32 and stmfx drivers - vrefbuf: fix a possible overshoot when re-enabling
2020-07-07Merge tag 'u-boot-atmel-2020.10-a' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-atmel First set of u-boot-atmel features for 2020.10 cycle
2020-07-07arm64: issue ISB after updating system registersVolodymyr Babchuk
ARM Architecture reference manual clearly states that PE pipeline should be flushed after changes to some system registers. Refer to paragraph "B2.3.5 Memory Barriers" at page B2-92 of "Arm Architecture Reference Manual ARMv8 for ARMv8-A Architecture Profile" (ARM DDI 0487B.a). Failing to issue instruction synchronization barrier can lead to spurious errors, like synchronous exception when accessing FPU registers. This is very prominent on CPUs with long instruction pipeline, like ARM Cortex A72. This change fixes the following U-Boot panic: "Synchronous Abort" handler, esr 0x1fe00000 elr: 00000000800948cc lr : 0000000080091e04 x0 : 00000000801ffdc8 x1 : 00000000000000c8 x2 : 00000000800979d4 x3 : 00000000801ffc60 x4 : 00000000801ffd40 x5 : ffffff80ffffffd8 x6 : 00000000801ffd70 x7 : 00000000801ffd70 x8 : 000000000000000a x9 : 0000000000000000 x10: 0000000000000044 x11: 0000000000000000 x12: 0000000000000000 x13: 0000000000000000 x14: 0000000000000000 x15: 0000000000000000 x16: 000000008008b2e0 x17: 0000000000000000 x18: 00000000801ffec0 x19: 00000000800957b0 x20: 00000000000000c8 x21: 00000000801ffdc8 x22: 000000008009909e x23: 0000000000000000 x24: 0000000000000000 x25: 0000000000000000 x26: 0000000000000000 x27: 0000000000000000 x28: 0000000000000000 x29: 00000000801ffc50 Code: a94417e4 a90217e4 a9051fe6 a90617e4 (3d801fe0) While executing instruction str q0, [sp, #112] in vsnprintf() prologue. This panic was observed only on Cortex A72 so far. This patch places ISBs on other strategic places as well. Also, this probably is the right fix for the issue workarounded in the commit 45f41c134baf ("ARM: uniphier: add weird workaround code for LD20") Reported-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com> Suggested-by: Julien Grall <julien.grall.oss@gmail.com> Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> CC: Tom Rini <trini@konsulko.com> CC: Masahiro Yamada <yamada.masahiro@socionext.com> CC: Stefano Stabellini <sstabellini@kernel.org> Reviewed-by: Julien Grall <julien@xen.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-07stm32mp1: use the command env info in env_checkPatrick Delaunay
Activate CMD_NVEDIT_INFO and use the new command "env info -d -p -q" to automatically save the environment on first boot. This patch allows to remove the env_default variable. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-07arm: stm32mp: protect DBGMCU_IDC access with BSECPatrick Delaunay
As debugger must be totally closed on Sec closed chip, the DBGMCU_IDC register is no more accessible (self hosted debug is disabled with OTP). This patch adds a function bsec_dbgswenable() to check if the DBGMCU registers are available before to access them: BSEC_DENABLE.DBGSWENABLE = self hosted debug status. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-07arm: stm32mp: stm32prog: add "Device Name" in iproduct during DFU USB ↵Patrick Delaunay
enumeration Add "Device Name" in iproduct during DFU USB enumeration to have this information in STM32CubeProgrammer trace (this tools is compatible with @Name since v2.3) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-07ARM: dts: stm32mp1: use OPP information for PLL1 settings in SPLPatrick Delaunay
This patch allows to switch the CPU frequency to 800MHz on the ST Microelectronics board (DK1/DK2 and EV1) or dh electronics SOM using the STM32MP15x SOC and when it is supported by the HW (for STM32MP15xD and STM32MP15xF). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-07board: st: stpmic1: add function stpmic1_initPatrick Delaunay
Add a function stmpic_init to early initialize the PMIC STPMIC1 - keep vdd on during the reset cycle (to avoid issue when backup battery is absent) - Check if debug is enabled to program PMIC according to the bit This patch allows to remove the compilation of spl.c file from stm32mp1 board in dh_stm32mp1. CONFIG_SPL_BOARD_INIT is removed as the new function is called earlier in SPL, in the function board_early_init_f. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-07arm: stm32mp: add weak function to save vddcorePatrick Delaunay
Add a weak functions to save the vddcore voltage value provided in the OPP node when the clock tree is initialized. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-07ARM: dts: stm32: add cpufreq support on stm32mp15xPatrick Delaunay
This commit adds cpufreq support on stm32mp15x SOC. STM32 cpufreq uses operating points V2 bindings (no legacy). Nvmem cells have to be used to know the chip version and then which OPPs are available. Note that STM32 cpufreq driver is mainly based on "cpufreq-dt" driver. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
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