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2019-10-08Merge tag 'u-boot-atmel-2020.01-a' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-atmel First set of u-boot-atmel features and fixes for 2020.01 cycle The feature set includes support for two new boards from Microchip AT91: The sama5d27_wlsom1_ek , an evaluation kit which includes the SAMA5D2 SOC packaged in a 256 MB LPDDR2 SIP, on a SOM including wireless, which is placed on evaluation kit with sd-card, ethernet, LCD, Camera sensor, QSPI, etc The sam9x60ek, an evaluation kit for the new SoC based on ARM926j , the SAM9X60 . The evaluation kit includes NAND flash, QSPI, Ethernet, Audio, Camera sensor connector, etc. The full support for sam9x60ek will come at a later time. There are still missing bits regarding the clock support and power management controller.
2019-10-08Merge tag 'efi-2020-01-rc1' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for efi-2020-01-rc1 The major corrections in this pull request are: Fixes for the SetVariable() boot service. Device path node for NVMe drives. Disable CONFIG_CMD_NVEDIT by default.
2019-10-08ARM: dts: at91: sam9x60ek: add onewire supportEugen Hristev
Add support for onewire memory. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2019-10-08ARM: dts: at91: sam9x60: add onewire nodeEugen Hristev
Add onewire node for w1 support. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2019-10-08ARM: dts: at91: sam9x60ek: Enable qspi nodeTudor Ambarus
The sam9x60 qspi controller uses 2 clocks, one for the peripheral register access, the other for the qspi core and phy. Both are mandatory. Enable the qspi node together with the SST26VF064B qspi nor flash memory. Booting from the QSPI NOR flash is now possible. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-10-08ARM: at91: Add SFR definitionsTudor Ambarus
sama5's SFR has at offset 0x04 the DDR Configuration Register, while sam9x60's SFR contains the EBI Chip Select Register. Add a union to reconcile both boards. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-10-08ARM: at91: Rename sama5_sfr.h to at91_sfr.hTudor Ambarus
The Special Function Registers (SFR) are present in sam9x5 and sam9x60 too, rename sama5_sfr to at91_sfr.h. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-10-08board: atmel: Add sam9x60ek boardSandeep Sheriker Mallikarjun
Add new board SAM9X60-EK using the ARM926 SAM9X60 SoC. Signed-off-by: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com> [tudor.ambarus@microchip.com: - fix number of DRAM banks: One DDR2-SDRAM (W972GG6KB 2 Gbit = 16 Mbit x 16 x 8 banks] - drop SPL related macros - drop memtest macros - drop CONFIG_SPI_BOOT, CONFIG_SYS_USE_DATAFLASH related macros - drop inclusion of asm/arch/at91sam9_smc.h] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-10-08ARM: dts: at91: sam9x60: Add macb0 Ethernet controllerNicolas Ferre
Add Ethernet controller to dtsi file and enable it on sam9x60ek platform connected with rmii. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2019-10-08ARM: dts: Add dts files for sam9x60ekSandeep Sheriker Mallikarjun
add device tree files for sam9x60ek board with below changes. - Add initial device nodes (pmc, pinctrl, sdhc, dbgu & pit) - Add the reg property for the pinctrl node. - Add the "u-boot,dm-pre-reloc" property to determine which nodes are used by the board_init_f stage. Signed-off-by: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com> [prasanthi.chellakumar@microchip.com: fix style/whitespace issues] Signed-off-by: Prasanthi Chellakumar <prasanthi.chellakumar@microchip.com> [nicolas.ferre@microchip.com: - fix gclk, - fix pio/pinctrl controller definition and allow to have more than only PIOA for this SoC, - removing pinctrl address] Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> [claudiu.beznea@microchip.com: - use SAM9X60's compatible for pinctrl - add drive strength and slew rate options for SDMMC0 pins.] Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> [tudor.ambarus@microchip.com: - u-boot,dm-pre-reloc property in dedicated file, - fix pit len, starts from 0xFFFFFE40 and it is of len 0x10] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-10-08ARM: at91: Add sam9x60 socSandeep Sheriker Mallikarjun
Add new Microchip sam9x60 SoC based on an ARM926. Signed-off-by: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com> [tudor.ambarus@microchip.com: fix SFR definition] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-10-08ARM: dts: at91: sama5d27_wlsom1: add hlcdc nodeEugen Hristev
Add node for hlcld for u-boot logo display at boot. This is compatible with the Precision Design Associates (PDA) TM5000 screen. Timings are compatible with simple panel from Linux, panel name is pda_91_00156_a0 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2019-10-08ARM: dts: at91: sama5d27_wlsom1_ek: add support for qspiEugen Hristev
Add node for qspi1 memory connected on the wlsom Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2019-10-08ARM: dts: at91: sama5d2: add seq for qspi1Eugen Hristev
qspi1 does not have an alias/seq number. This is required for SPL default SF bus booting for the boards that have this SoC Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2019-10-08board: atmel: sama5d2_wlsom1_ek: add SPL supportEugen Hristev
Add support for SPL for this board: DRAM initialization, PMC initialization, MMC boot. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2019-10-08ARM: at91: mpddrc: add lpddr2 initialization procedureEugen Hristev
Implement the lpddr2 initialization procedure for at91 mpddrc multi-port ddram controller. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2019-10-08board: laird: wb50n: use configure_ddrcfg_input_buffersEugen Hristev
Replace code with new function configure_ddrcfg_input_buffers from SFR mach driver. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2019-10-08ARM: at91: sfr: implement DDR input buffers open functionEugen Hristev
Add a function in SFR implementation that will open the DDR input buffers. This can be called at DRAM initialization time. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2019-10-08ARM: at91: sfr: convert to KconfigEugen Hristev
This converts the at91 sfr to Kconfig Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2019-10-08board: atmel: add sama5d27_wlsom1_ek boardNicolas Ferre
Add support for the SAMA5D27-WLSOM1-EK. It's based on the Microchip WireLess SoM which contains the SAMa5D27 LPDDR2 2Gbits SiP. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> [eugen.hristev@microchip.com]: added u-boot specific dtsi and ported to 2019.10 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2019-10-08ARM: at91: Add the chip ID for SAMA5D2 LPDDR2 SiPNicolas Ferre
The SAMA5D2 LPDDR2 SiP (System in Package) is added for SoC identification. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2019-10-07NET: DW: fix regression for ARC boardsEugeniy Paltsev
The commit 642b80d256e ("net: designware: drop compatible altr, socfpga-stmmac") breaks designware ethernet for all ARC boards. It removes "altr, socfpga-stmmac" compatible from "drivers/net/designware.c" without changing compatible in the boards which use it. Fix that by adding "snps,arc-dwmac-3.70a" compatible string to "drivers/net/designware.c" and using it in ARC boards device tree. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2019-10-06Revert "ARM: tegra: reserve unmapped RAM so EFI doesn't use it"Mian Yousaf Kaukab
This reverts commit 0797f7f0b7e1d7853e2842ddc235ffef139fa792. Tegra specific solution is not required any more as efi core has been made aware of ram_top with the following commit: 7b78d6438a efi_loader: Reserve unaccessible memory Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de>
2019-10-05Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
- ARM: dts: rmobile: Restore increase off-on delay on the SD Vcc regulator
2019-10-04ARM: dts: imx6q-logicpd: Add missing imx6q-logicpd-u-boot for SPLAdam Ford
The SPL device tree is missing the entires for gpio1, uart1, usdhc1 and usdhc2. This creates the missing imx6q-logicpd-u-boot.dtsi file which will enable these functions so SPL can properly setup UART, detect microSD card, and startup. Fixes: 8f4691e31a18 ("ARM: imx6q_logic: With SPL_OF_CONTROL enabled, remove MMC init") Signed-off-by: Adam Ford <aford173@gmail.com>
2019-10-04board: ti: am654: Disable TRNG node for HS devicesAndrew F. Davis
On HS devices the access to TRNG is restricted on the non-secure ARM side, disable the node in DT to prevent firewall violations. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-04arm: K3: Increase default SYSFW image size allocationAndrew F. Davis
The memory allocated to store the FIT image containing SYSFW and board configuration data is statically defined to the largest size expected. This was 269000 bytes but now needs to be grown to 276000 to make room for the signatures attached to the board configuration data on High Security devices. Signed-off-by: Andrew F. Davis <afd@ti.com>
2019-10-01x86: zImage: Propagate acpi_rsdp_addr to kernel via boot parametersAndy Shevchenko
This is reincarnation of the U-Boot commit 3469bf4274540d1491d58e878a9edc0bdcba17ac Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Date: Wed Jan 10 19:40:15 2018 +0200 x86: zImage: Propagate acpi_rsdp_addr to kernel via boot parameters after upstream got eventually the Linux kernel commit e6e094e053af75cbc164e950814d3d084fb1e698 Author: Juergen Gross <jgross@suse.com> Date: Tue Nov 20 08:25:29 2018 +0100 x86/acpi, x86/boot: Take RSDP address from boot params if available Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-30ARM: dts: rmobile: Restore increase off-on delay on the SD Vcc regulatorMarek Vasut
This patch restores commit c49d0ac38a76 ("ARM: dts: rmobile: Increase off-on delay on the SD Vcc regulator"), which was accidentally dropped during DT resync in commit 317d13ac6307 ("ARM: dts: rmobile: Synchronize Gen3 DTs with Linux 5.0"). Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Fixes: 317d13ac6307 ("ARM: dts: rmobile: Synchronize Gen3 DTs with Linux 5.0")
2019-09-28rockchip: make_fit_atf.py: fix .its generation for a single atf imageHeiko Stuebner
The commit 619f002db864 ("rockchip: make_fit_atf.py: fix loadables property set error") fixed the double-loading of the primary atf-image, but didn't take into account that there may be rare atf images with only that main section present. Right now this will result in a broken its due to the loadables section not getting closed correctly, so fix that by adapting the guards around the loop. The guards now protect against 0 segments when the bl31 binary doesn't contain any section and 1 segment when only a core atf section is present. Fixes: 619f002db864 ("rockchip: make_fit_atf.py: fix loadables property set error") Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2019-09-28rockchip: misc: read the correct number of bytes from the efuseHeiko Stuebner
Originally the cpuid var the value gets read into was defined as u8 cpuid[RK3399_CPUID_LEN]; hence the sizeof(cpuid) would return the correct the correct number of array elements. With the move to a separate function cpuid becomes a pointer and sizeof(cpuid) hence returns the pointer size - 8 in the arm64 case. We do have the actual id length available as function param so use it for actual amount of bytes to read. Fixes: 04825384999f ("rockchip: rk3399: derive ethaddr from cpuid") Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2019-09-19rockchip: rk3288-tinker: Attach missing peripherals at SPLMichael Trimarchi
Tinker board needs to mux all the sdmmc gpio and activate the regulator connected to bank 7. Remove all the bank that are not in use and mark them as dm,spl so-that it would initialize at SPL. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2019-09-19rockchip: spi-boot-order: Trival fix to newline missingJagan Teki
newline \n was missed in fdt_path_offset, error loop. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2019-09-19rockchip: rk3288: vyasa: Drop ROCKCHIP_BROM_HELPER selectionJagan Teki
ROCKCHIP_BROM_HELPER is selected as if TPL/SPL ROCKCHIP_BACK_TO_BROM has been defined, so drop the explicit enablement for vyasa board. This change is supposed to missed during config move to other locations, and missed to drop the same. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2019-09-16Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini
- Add emmc hs200 support - Few bug fixes related to serdes, I2C, ethernet, etc
2019-09-15Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
2019-09-14sh: r2dplus: Fix missing PCI rangeMarek Vasut
Add missing PCI range for translating DRAM to bus addresses. This fixes e.g. PCI NIC interface and allows network to work in QEMU. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-09-14sh: Fix SH4 build with GCC versions without -m4-nofpuMarek Vasut
Pass -m4 instead of -m4-nofpu to GCC versions which do not support the -m4-nofpu option. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-09-14sh: Fix incorrect linking with new binutilsMarek Vasut
Since binutils 2.30 , the resulting U-Boot binary was incorrectly linked against address 0 instead of text base, fix it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-09-13ARM: dts: dra74x: Fix iodelay configuration for mmc3Faiz Abbas
According to the latest am572x[1] and dra74x[2] data manuals, mmc3 default, hs, sdr12 and sdr25 modes use iodelay values given in MMC3_MANUAL1. Set the MODE_SELECT bit for these so that manual mode is selected and correct iodelay values are configured. [1] http://www.ti.com/lit/ds/symlink/am5728.pdf [2] http://www.ti.com/lit/ds/symlink/dra746.pdf Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-09-13arm: k3: Use get_ti_sci_handle() where ever possibleLokesh Vutla
Instead of calling uclass apis everywhere, use get_ti_sci_handle() when ever ti_sci is needed. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-09-13arm: k3: Fix getting ti_sci handleLokesh Vutla
API get_ti_sci_handle() is relying on the device-tree node name to be "dmsc" for probing the ti_sci device. But with the introduction of debug messages for dmsc, the node name changed to dmsc@44083000. Because of this ti_sci is never probed cause a boot failure. Instead of relying on device-tree node name, use the first available firmware node for probing ti_sci. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-09-13ARM: omapl138_lcdk: Enable DM_GPIO and DM and GPIO CommandsAdam Ford
The da8xx GPIO driver is available with DM_GPIO support. This patch enables the CMD_GPIO, CMD_DM, and DM_GPIO and DA8XX_GPIO. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-09-13arm: am437x: cm-t43: Add device tree, enable OF_CONTROLSuniel Mahesh
Add device tree from Linux for driver model conversion and enable OF_CONTROL. This will remove the following compile warning: ================================================== Device Tree Source is not correctly specified. Please define 'CONFIG_DEFAULT_DEVICE_TREE' or build with 'DEVICE_TREE=<device_tree>' argument =================================================== Target was compile tested, build was clean. Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
2019-09-12armv8: ls1028a: Updated serdes configuration for 0x13BBHou Zhiqiang
In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12armv8: fsl-layerscape: Fix typo in Layerscape PCIe config entryHou Zhiqiang
The correct config entry is CONFIG_PCIE_LAYERSCAPE and this typo results in skipping the fixup of Linux PCIe DT nodes. Also enable the fixup when Layerscape Gen4 controller driver is enabled. Fixes: 4da0e52c9dc0 (armv8: fsl-layerscape: fix config dependency for layerscape pci code) Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12armv8: fsl-layerscape: Update I2C clock dividerChuanhua Han
By default, i2c input clock is programmed at platform clk / 2 in u-boot, but this is not correct for all the platforms, Update I2C clock divider's default values as per SoC (LS1012A, LS1028A, LX2160A and LS1088A). Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12armv8: ls1028a: configure PMU's PCTBENR to enable WDTThomas Schaefer
The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12arm: dts: ls1028a-qds: define the MDIO MUXAlex Marginean
Add the device-tree structure describing the MUX in board dts. QDS board has an on-board RGMII PHY and 4 slots for extension cards. All these can be accessed over MDIO through a MDIO MUX controlled over I2C. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12dts: armv8: add emmc hs200 support for ls1028ardbYinbo Zhu
Add emmc hs200 support for ls1028ardb Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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