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2019-05-23stm32mp1: psci: add synchronization with ROM codePatrick Delaunay
Use SGI0 interruption and TAMP_BACKUP_MAGIC_NUMBER to synchronize the core1 boot sequence requested by core0 in psci_cpu_on(): - a initial interruption is needed in ROM code after RCC_MP_GRSTCSETR_MPUP1RST (psci_cpu_off) - the ROM code set to 0 the 2 registers + TAMP_BACKUP_BRANCH_ADDRESS + TAMP_BACKUP_MAGIC_NUMBER when magic is not egual to BOOT_API_A7_CORE0_MAGIC_NUMBER This patch solve issue for cpu1 restart in kernel. echo 0 > /sys/devices/system/cpu/cpu1/online echo 1 > /sys/devices/system/cpu/cpu1/online Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23stm32mp1: cosmetic: bsec: reorder include filesPatrick Delaunay
Reorder the include files in alphabetic order. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23stm32mp1: migrate PREBOOT to KconfigPatrick Delaunay
Use Kconfig to activate CONFIG_PREBOOT (empty by default). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23stm32mp1: Move ENV_SIZE and ENV_OFFSET to KconfigPatrick Delaunay
Add arch stm32mp for ENV migration step and drop more items from include/configs/xxx.h. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23stm32mp1: Move config SYS_MALLOC_LEN to KconfigPatrick Delaunay
This patch moves the the config SYS_MALLOC_LEN to Kconfig as it is already done for zynq arch in commit 01aa5b8f0503 ("Kconfig: Move config SYS_MALLOC_LEN to Kconfig for zynq") Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23arch: powerpc: add eSDHC node to t2080qds dtsYinbo Zhu
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22arm: dts: fsl-ls1028a: add sp805 watchdog nodeQiang Zhao
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE.Udit Agarwal
ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22ARM: dts: Freescale: Add ecc addr for sata nodePeng Ma
Move the ecc addr from driver to dts. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22armv8: ls1028aqds: Add support of LS1028AQDSYuantian Tang
LS1028AQDS Development System is a high-performance computing, evaluation, and development platform that supports LS1028A QorIQ Architecture processor. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang yuantian <andy.tang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22armv8: ls1028ardb: Add support for LS1028ARDBYuantian Tang
LS1028A is an ARMv8 implementation. LS1028ARDB is an evaluation platform that supports the LS1028A family SoCs. This patch add basic support of the platform. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22armv8: ls1028a: Add NXP LS1028A SoC supportYuantian Tang
Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22armv8: lx2160a: add PCIe controller DT nodesHou Zhiqiang
The LX2160A integrated 6 PCIe Gen4 controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22kconfig: add dependency PCIE_LAYERSCAPE_GEN4 for FSL_PCIE_COMPATHou Zhiqiang
The LX2160A PCIe is using driver PCIE_LAYERSCAPE_GEN4 instead of PCIE_LAYERSCAPE. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22armv8: lx2160a: add MMU table entries for PCIeHou Zhiqiang
The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22armv8: fsl-layerscpae: correct the PCIe controllers' region sizeHou Zhiqiang
The LS2080A has 8GB region for each PCIe controller, while the other platforms have 32GB. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22armv8: layerscape: use PCIe address macro for precompile PCIe MMU entryHou Zhiqiang
Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-21ARM: rmobile: Add recovery SPL for R-Car Gen3Marek Vasut
Build an SPL which can be started via SCIF download mode on R-Car Gen3 and allows loading and executing U-Boot uImage with the next stage code. This is also useful for starting e.g. ATF BL2, which inits the hardware and returns to the U-Boot SPL, which can then load e.g. U-Boot proper. The H3, M3-W, M3-N SoCs have plenty of SRAM for storing the U-Boot SPL while the payload, e.g. ATF BL2, executes, so there is no problem here. However, E3 and D3 have much less SRAM, hence the loader uses a trick where it copies itself beyond the area used by BL2 and executes from there. That area is 32kiB large and not enough to hold U-Boot SPL, BSS, stack and malloc area, so the later two are placed at +0x4000 offset from start of SRAM, another area not used by ATF BL2. To make things even more complicated, the SCIF loader cannot load to the upper 32kiB of the SRAM directly, hence the copying approach. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-21Merge git://git.denx.de/u-boot-mpc83xxTom Rini
- Update MPC83xx platform support to current best practices, etc.
2019-05-21Merge tag 'video-for-2019.07-rc3' of git://git.denx.de/u-boot-videoTom Rini
- update for using splashfile instead of location->name when loading the splash image from a FIT - updates for loading internal and external splash data from FIT - DM_GPIO/DM_VIDEO migration for mx53 cx9020 board - fix boot issue on mx6sabresd board after DM_VIDEO migration - increase the max preallocated framebuffer BPP to 32 in ipuv3 driver to prepare for configurations with higher color depth - allow to use vidconsole_put_string() in board code for text output on LCD displays
2019-05-21mpc83xx: Add gazerbeam boardDirk Eibach
The gdsys gazerbeam board is based on a Freescale MPC8308 SOC. It boots from NOR-Flash, kernel and rootfs are stored on SD-Card. On board peripherals include: - 2x 10/100 Mbit/s Ethernet (optional) Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21gazerbeam: Add u-boot specific dts include fileMario Six
Add a U-Boot specific dts file, which encapsulates the needed modifications to the Gazerbeam Linux device tree. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21gazerbeam: Import Linux DTMario Six
Import the Linux device tree for the Gazerbeam board. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21mpc83xx: Define _end symbolMario Six
To support OF_EMBED, the MPC83xx architecture has to define the "_end" symbol to correctly access the appended DT. Fortunately, MPC8xx already defines the symbol, and the linker script is quite similar to that of MPC83xx, so copy this approach for MPC83xx. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21powerpc: Simplify processor.hMario Six
Lots of stuff in processor.h was taken verbatim from the Linux kernel. It was never synced, so most of it was removed or changed in the kernel since it was imported. Remove all the stuff that is unused in the current U-Boot sources; should anybody feel the need to re-sync with the kernel, they can do it later on. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21mpc83xx: Use pre-defined asm functionsMario Six
For a lot of inline assembly calls in the mpc8xxx and mpc83xx directories, we already have convenient pre-defined helper functions, but they're not used, resulting in hard-to-read code. Use these helper functions where ever possible and useful. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21mpc83xx: Replace ppcDWstore with inline assemblyMario Six
ppcDWstore/ppcDWload are hardly used by any board, but since they're implemented in start.S, they're always present in every U-Boot image, even if they're not needed. Re-implement these fuctions in C with inline assembly, so that the compiler can decide when to actually include them. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21mpc83xx: Don't define cpu_eth_init for DM ethMario Six
Don't use the legacy method of initializing the ethernet controller on MPC83xx when DM is active. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21mpc83xx: Add arch clock.h to make SDHC workMario Six
The fsl-esdhc driver can be used for the SDHC functionality on MPC83xx, but it needs some additional definitions. Add a clock.h file, so we can use the driver for MPC83xx. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21mpc83xx: Get rid of CONFIG_SYS_DDR_SDRAM_BASEMario Six
CONFIG_SYS_DDR_SDRAM_BASE is set to the same value as CONFIG_SYS_SDRAM_BASE on all existing boards. Just use CONFIG_SYS_SDRAM_BASE instead. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21mpc83xx: Migrate CONFIG_LCRR_* to KconfigMario Six
Migrate the CONFIG_LCRR_* settings to Kconfig. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21mpc83xx: Migrate SPCR to KconfigMario Six
Migrate the SPCR setting to Kconfig. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21mpc83xx: Migrate arbiter config to KconfigMario Six
Migrate the arbiter configuration to Kconfig. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21mpc8308: Migrate system io config to KconfigMario Six
Migrate the system IO configuration setting to Kconfig. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21mpc83xx: Migrate CONFIG_SYS_IMMR to KconfigMario Six
Migrate CONFIG_SYS_IMMR to Kconfig for MPC83xx. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21mpc83xx: Migrate HID config to KconfigMario Six
Mirate the HID configuration settings to Kconfig. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21mpc83xx: Prepare usage of DM gpio driverMario Six
The MPC85xx GPIO driver was converted to handle a broader range of SoCs. Prepare the MPC83xx code for usage of this driver. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21powerpc: mpc83xx: fdt: Use get_serial_clock()Mario Six
Replace the hard-coded CONFIG_SYS_NS16550_CLK value for the FDT fixup with the previously introduced get_serial_clock function This will make it possible to activate DM for serial devices on MPC83xx later on. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21powerpc: mpc83xx: Implement get_serial_clock()Mario Six
DM serial drivers on PowerPC determine their clock frequency via the get_serial_clock function. This function is not Implemented yet for MPC83xx. This patch Implements the function so that DM serial drivers work on MPC83xx. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21powerpc: mpc83xx: Fix MPC8308 IMMR memory layoutMario Six
The MPC8308 has two I2C controllers, but no PCI controller. Fix the register map layout for this SoC. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21mpc83xx: Migrate CONFIG_SYS_{BR, OR}*_PRELIM to KconfigMario Six
Migrate the BR/OR settings to Kconfig. These must be known at compile time, so cannot be configured via DT. Configuration of this crucial variable should still be somewhat comfortable. Hence, make its fields configurable in Kconfig, and assemble the final value from these. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21mpc83xx: Migrate LBLAW_* to KconfigMario Six
The LBLAW_* values determine the window configuration of the memory controller. Hence, they must be known at compile time, and cannot be implemented in the DT mechanism. Configuration of this crucial variable should still be somewhat comfortable. Hence, make its fields configurable in Kconfig, and assemble the final value from these. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21mpc83xx: Migrate BATS config to KconfigMario Six
The BATs (block address translation registers) determine the initial memory window mappings. Hence, they must be known at compile time and cannot be implemented in the DT mechanism. Configuration of this crucial variable should still be somewhat comfortable. Hence, make its fields configurable in Kconfig, and assemble the final value from these. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21powerpc: Migrate HIGH_BATS to KconfigMario Six
Migrate the CONFIG_HIGH_BATS variable to Kconfig. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21mpc83xx: pcie: Read the clock from registersMario Six
The MPC83xx DM timer driver disables arch.pciexp*_clk, and uses clk_get_rate instead. But the legacy MPC83xx PCIe driver still uses arch.pciexp*_clk for the clock. Hence, read the PCIe clock from the registers in the legacy MPC83xx PCIe driver. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21mpc83xx: Kconfig: Migrate HRCW to KconfigMario Six
The HRCW (hardware reset configuration word) is a constant that must be hard-coded into the boot loader image. So, it must be available at compile time, and cannot be migrated to the DT mechanism, but has to be kept in Kconfig. Configuration of this crucial variable should still be somewhat comfortable. Hence, make its fields configurable in Kconfig, and assemble the final value from these. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21mpc83xx: Get rid of CONFIG_83XX_CLKINMario Six
MPC83xx uses CONFIG_83XX_CLKIN instead of CONFIG_SYS_CLK_FREQ to set the system clock. To migrate the architecture, we can replace CONFIG_83XX_CLKIN with CONFIG_SYS_CLK_FREQ. To do this * replace all occurrences of CONFIG_83XX_CLKIN with CONFIG_SYS_CLK_FREQ * set CONFIG_SYS_CLK_FREQ to the old value of CONFIG_83XX_CLKIN in all MPC83xx config files Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21mpc83xx: Replace CONFIG_83XX_CLKIN in calculationsMario Six
CONFIG_SYS_CLK_FREQ is the standard way to set the system clock frequency. On MPC83xx, CONFIG_83XX_CLKIN is used for this purpose. Hence, the obvious way is to replace CONFIG_83XX_CLKIN with CONFIG_SYS_CLK_FREQ. A few MPC83xx boards use the CONFIG_83XX_CLKIN variable for computing CONFIG_SYS_NS16550_CLK. This makes it harder to replace CONFIG_83XX_CLKIN. But the value of the multiplicator can be read from the SPMR register. Hence, replace the static calculations with a call to a new get_bus_freq function, as other architectures do. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21mpc83xx: Migrate legacy PCI options to KconfigMario Six
The MPC83xx include files contain some settings of the PCI subsystem. Migrate these to Kconfig until a proper DM PCI driver exists. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21mpc83xx: Make distinct MPC8349EMDS_SDRAM boardMario Six
The MPC8349EMDS config file contains config options to enable SDRAM support. To keep this ability after the Kconfig migration, create a new MPC8349EMDS_SDRAM board that enables the SDRAM support and remove the SDRAM support from the original board. Signed-off-by: Mario Six <mario.six@gdsys.cc>
generated by cgit (git 2.34.1) at 2024-12-25 13:38:55 +0000