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2018-12-19bmips: enable dgnd3700v2 enet supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6362: add support for bcm6368-enetÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: enable ar-5387un enet supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6328: add support for bcm6368-enetÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: enable wap-5813n enet supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6368: add support for bcm6368-enetÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: enable nb4-ser enet supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: enable hg556a enet supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6358: add support for bcm6348-enetÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: enable ct-5361 enet supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6348: add support for bcm6348-enetÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: enable f@st1704 enet supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6338: add support for bcm6348-enetÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6318: add bcm6348-iudma supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm63268: add bcm6348-iudma supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6362: add bcm6348-iudma supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6328: add bcm6348-iudma supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6368: add bcm6348-iudma supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6358: add bcm6348-iudma supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6348: add bcm6348-iudma supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6338: add bcm6348-iudma supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-18riscv: Remove ae350.dtsBin Meng
This is not used by any board. Remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: bootm: Change to use boot_hart from global dataBin Meng
Avoid reading mhartid CSR directly, instead use the one we saved in the global data structure before. With this patch, BBL no longer needs to be hacked to provide the mhartid CSR emulation for S-mode U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Save boot hart id to the global dataBin Meng
At present the hart id passed via a0 in the U-Boot entry is saved to s0 at the beginning but does not preserve later. Save it to the global data structure so that it can be used later. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Adjust the _exit_trap() position to come before handle_trap()Bin Meng
With this change, we can avoid a forward declaration. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Return to previous privilege level after trap handlingBin Meng
At present the trap handler returns to hardcoded M-mode/S-mode. Change to returning to previous privilege level instead. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Fix context restore before returning from trap handlerBin Meng
sp cannot be loaded before restoring other registers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Move trap handler codes to mtrap.SBin Meng
Currently the M-mode trap handler codes are in start.S. For future extension, move them to a separate file mtrap.S. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Do some basic architecture level cpu initializationBin Meng
In arch_cpu_init_dm() do some basic architecture level cpu initialization, like FPU enable, etc. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Add indirect stringification to csr_xxx opsBin Meng
With current csr_xxx ops, we cannot pass a macro to parameter 'csr', hence we need add another level to allow the parameter to be a macro itself, aka indirect stringification. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Update supports_extension() to use desc from cpu driverBin Meng
This updates supports_extension() implementation to use the desc string from the cpu driver whenever possible, which avoids the reading of misa CSR for S-mode U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Add exception codes for xcause registerBin Meng
This adds all exception codes in encoding.h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Add CSR numbersBin Meng
The standard RISC-V ISA sets aside a 12-bit encoding space for up to 4096 CSRs. This adds all known CSR numbers as defined in the RISC-V Privileged Architecture Version 1.10. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Remove non-DM version of print_cpuinfo()Bin Meng
With DM CPU driver, the non-DM version of print_cpuinfo() is no longer needed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Probe cpus during bootBin Meng
This calls cpu_probe_all() to probe all available cpus. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Enlarge the default SYS_MALLOC_F_LENBin Meng
Increase the heap size for the pre-relocation stage, so that CPU driver can be loaded. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: qemu: Add platform-specific Kconfig optionsBin Meng
Add the QEMU RISC-V platform-specific Kconfig options, to include CPU and timer drivers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Implement riscv_get_time() API using rdtime instructionAnup Patel
This adds an implementation of riscv_get_time() API that is using rdtime instruction. This is the case for S-mode U-Boot, and is useful for processors that support rdtime in M-mode too. Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-12-18riscv: Add a SYSCON driver for SiFive's Core Local InterruptorBin Meng
This adds U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT). The CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. This driver implements the riscv_get_time() API as required by the generic RISC-V timer driver, as well as some other APIs that are needed for handling IPI. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Introduce a Kconfig option for machine modeAnup Patel
So far we have a Kconfig option for supervisor mode. This adds an option for the machine mode. Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-12-18riscv: ax25: Hide the ax25-specific Kconfig optionBin Meng
There is no need to expose RISCV_NDS to the Kconfig menu as it is an ax25-specific option. Introduce a dedicated Kconfig option for the cache ops of ax25 platform and use that to guard the cache ops. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
2018-12-18riscv: qemu: Create a simple-bus driver for the soc nodeBin Meng
To enumerate devices on the /soc/ node, create a "simple-bus" driver to match "riscv-virtio-soc". Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: add Kconfig entries for the code modelLukas Auer
RISC-V has two code models, medium low (medlow) and medium any (medany). Medlow limits addressable memory to a single 2 GiB range between the absolute addresses -2 GiB and +2 GiB. Medany limits addressable memory to any single 2 GiB address range. By default, medlow is selected for U-Boot on both 32-bit and 64-bit systems. The -mcmodel compiler flag is selected according to the Kconfig configuration. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> [bmeng: adjust to make medlow the default code model for U-Boot] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-16Merge tag 'for-master-20181216' of git://git.denx.de/u-boot-rockchipTom Rini
Improvements and fixes or u-boot-rockchip: - new board: adds rv1108-elgin-r1 board support - rk3288-evb: dts: remove 'vmmc' from emmc node - rk3399-puma: dts: remove obsolete DTS node 'vcc5v0_host'
2018-12-16ARM: rockchip: Add rv1108-elgin-r1 board supportOtavio Salvador
Add the initial support for Elgin R1 board, which is based on the RV1108 SoC and has the following features currently supported in U-Boot: - UART - eMMC - USB Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-12-15Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini
- Second half of the USB Gadget DM conversion
2018-12-15rockchip: rk3288-evb: dts: remove 'vmmc' from emmc nodeKever Yang
This is a sync with kernel mainline dts. The U-Boot eMMC does not need to care about the power for Rockchip SoCs, because if the board is using eMMC, the power will default on (for bootrom), so the 'vmmc', 'vqmmc' is only useful for SD in U-Boot. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-12-15rockchip: rk3399-puma: Remove obsolete DTS node 'vcc5v0_host'.Christoph Muellner
vcc5v0_host and usbhub_enable share gpio4 RK_PA3, which is a problem during probing (the second probe will trigger a -EBUSY, when trying to get the gpio handle). An analysis of the situation shows, that both regulators are actually describing the same supply. This patch removes the (currenlty not successful probing) regulator vcc5v0_host from the DTS and adds the pinctrl-* setting to usbhub_enable. Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Reviewed-by: Phiilipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-12-15poplar: fix boot failure caused by serial driver changeShawn Guo
Commit 4687919684e0 ("serial: Remove DM_FLAG_PRE_RELOC flag in various drivers") essentially drops flag DM_FLAG_PRE_RELOC from serial_pl01x driver for Poplar platform, because the platform falls into the following strategy category made by the commit. Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for drivers that support both statically declared devices and configuration from device tree Before the commit lands, Poplar platform works by statically declaring pl011 serial device via U_BOOT_DEVICE() with DM_FLAG_PRE_RELOC flag set in the driver. But since Poplar also supports device configuration from device tree, the commit practically drops the flag for Poplar, and hence breaks the platform from booting. This patch changes platform code and device tree to initiate pl011 serial device from device tree rather than static declaration, so that above strategy about DM_FLAG_PRE_RELOC applies to Poplar, and therefore the reported boot failure gets fixed. Reported-by: Igor Opaniuk <igor.opaniuk@linaro.org> Fixes: 4687919684e0 ("serial: Remove DM_FLAG_PRE_RELOC flag in various drivers") Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org> Tested-by: Igor Opaniuk <igor.opaniuk@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-12-14arm: am33xx: Register USB controllers if DM_USB is used but not OF_CONTROLJean-Jacques Hiblot
When DM_USB is used, either the USB controllers are bound when the DTB is parsed (when OF_CONTROL is enabled) or they are bound using the U_BOOT_DEVICES() macro. In the later case, the platform data is passed in a struct ti_musb_platdata because it cannot be read from the DTB. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
generated by cgit (git 2.34.1) at 2025-02-02 09:35:03 +0000