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2017-09-29arm: dts: da850: Migrate da850-evm DTS files from Linux 4.13-RC5Adam Ford
A few small additional items are needed to support DM_SPI and DM_SERIAL, so those were added to da850-evm-u-boot.dtsi Signed-off-by: Adam Ford <aford173@gmail.com>
2017-09-28nds32: Fix io.h warning message about readbrick
It is caused from asm/io.h declare different input type. Signed-off-by: rick <rick@andestech.com>
2017-09-26arm: mvebu: fix boot from UART on ClearFog BaseBaruch Siach
The ClearFog Base boot from UART when setting the DIP switches to 01001. Unfortunately, the SPL code sometimes fails to detect the UART boot method at run-time. Add an alternative SAR UART boot value to fix this. Note that this alternative value is not documented (Armada 38x Hardware Specifications, Table 48). But experimentations showed it on the ClearFog Base. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
2017-09-26ARM: mvebu: handle unused DRAM banks with ECC enabledChris Packham
dram_ecc_scrubbing() had code to skip unused DRAM banks but it would not work because mvebu_sdram_bs() returns 0 and the code was subtracting 1 before checking the size. Remove the -1 from the bank size and the +1 from the total which will skip unused banks and still calculate the correct size. Put the -1 where it is needed for scrubbing via the xor engine. Reported-by: Joshua Scott <joshua.scott@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2017-09-26ARM: mvebu: add SAR frequency values for 1.8/2.0GHzChris Packham
The Armada-38x has 1.8GHz and 2.0GHz variants. Add entries for these variants to the sar_freq_tab. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2017-09-26ARM: mvebu: add additional information to board_add_ram_info()Joshua Scott
Display more information about the current RAM configuration. With these changes the output on a 88F6820 board is SoC: MV88F6820-A0 at 1600 MHz DRAM: 2 GiB (800 MHz, 32-bit, ECC not enabled) Signed-off-by: Joshua Scott <joshua.scott@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2017-09-26ARM: mvebu: Add SoC IDs for Marvell's integrated CPUsChris Packham
These SoCs are network packet processors (switch chips) with integrated ARMv7 cores. They share a great deal of commonality with the Armada-XP CPUs. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2017-09-26ARM: mvebu: Convert CONFIG_MVNETA to KconfigChris Packham
This converts the following to Kconfig: CONFIG_MVNETA Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2017-09-23Merge git://git.denx.de/u-boot-socfpgaTom Rini
2017-09-23ARM: socfpga: fix duplicate const specifier warningMasahiro Yamada
GCC 7.1 warns: duplicate ‘const’ declaration specifier [-Wduplicate-decl-specifier] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-09-22armv8: fsl: i2c: Put I2C related code under CONFIG_SYS_I2CSriram Dash
I2C code is put under CONFIG_SYS_I2C. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22armv8: fsl: ifc: Put IFC related code under CONFIG_FSL_IFCSriram Dash
IFC code is put under CONFIG_FSL_IFC Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22board/ls2081ardb: Update QSPI flash type from n25q512a to s25fs512sSantan Kumar
As per updated board design, different QSPI flash is connected on boards, hence change QSPI flash type from Micron n25q512a device to spansion s25fs512s device in dts and config. Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22armv8: fsl-layerscape: Put SATA code under SATA configsAshish Kumar
It is not necessary for every SoC to have 2 SATA controller. So put SATA1, SATA2 code under respective defines. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22arm: am33xx: Make pin multiplexing functions optionalFelix Brack
This patch provides default implementations of the two functions set_uart_mux_conf and set_mux_conf_regs. Hence boards not using them do not need to provide their distinct empty definitions. Signed-off-by: Felix Brack <fb@ltec.ch> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-22board: Add stm32h7 SoC, discovery and evaluation boards supportPatrice Chotard
This patch adds support for stm32h7 soc family, stm32h743 discovery and evaluation boards. For more information about STM32H7 series, please visit: http://www.st.com/en/microcontrollers/stm32h7-series.html Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22ARM: DTS: stm32: adapt stm32h7 dts files for U-bootPatrice Chotard
This patch adapts stm32h743 disco and eval dts files to match with U-boot requirements or add features wich are not yet upstreamed on kernel side : _ Add RCC clock driver node and update all clocks phandle accordingly. By default, on kernel side, all clocks was temporarly configured as a phandle to timer_clk waiting for a RCC clock driver to be available. On U-boot side, we now have a dedicated RCC clock driver, we can configured all clocks as phandle to this driver. All this binding update will be available soon in a kernel tag, as all the bindings have been acked by Rob Herring [1]. [1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html _ Align STM32H7 serial compatible string with the one which will be available in next kernel tag. The bindings has been acked by Rob Herring [2]. This compatible string will be usefull to add stm32h7 specific feature for this serial driver. [2] https://lkml.org/lkml/2017/7/17/739 _ Add gpio compatible and aliases for stm32h743 _ Add FMC sdram node with associated new bindings value to manage second bank (ie bank 1). _ Add missing HSI and CSI oscillators nodes needed by STM32H7 RCC clock driver. Clock sources could be: _ HSE (High Speed External) _ HSI (High Speed Internal) _ CSI (Low Power Internal) These clocks can be used as clocksource in some configuration. By default, HSE is selected as clock source. _ Set HSE to 25Mhz for stm32h743i-disco and eval board By default, the external oscillator frequency is defined at 25 Mhz in SoC stm32h743.dtsi file. It has been set at 125 Mhz in kernel DT temporarly waiting for RCC clock driver becomes available. As in U-boot we got a RCC clock driver, the real value of HSE clock can be used. _ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl, pwrcfg and gpio nodes. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22ARM: DTS: stm32: add stm32h743i-eval filesPatrice Chotard
This file is imported from linux kernel v4.13 Add device tree support for STM32H743 evaluation board. This board offers : _ STM32H743XIH6 microcontroller with 2 Mbytes of Flash memory and 1 Mbyte of RAM in TFBGA240+25 package _ 5.7” 640x480 TFT color LCD with touch screen _ Ethernet compliant with IEEE-802.3-2002 _ USB OTG HS and FS _ I2 C compatible serial interface _ RTC with rechargeable backup battery _ SAI Audio DAC _ ST-MEMS digital microphones _ 8-Gbyte (or more) SDIO3.0 interface microSD™ card _ 8Mx32bit SDRAM, 1Mx16bit SRAM and 8Mx16bit NOR Flash _ 1-Gbit Twin Quad-SPI NOR Flash _ Potentiometer _ 4 colored user LEDs _ Reset, wakeup, tamper or key buttons _ Joystick with 4-direction control and selector _ Board connectors : Power jack 3 USB with Micro-AB RS-232 communications Ethernet RJ45 FD-CAN compliant connection Stereo headset jack including analog microphone input 2 audio jacks for external speakers microSD™ card JTAG/SWD and ETM trace _ Expansion connectors: Extension connectors and memory connectors for daughterboard or wire-wrap board _ Flexible power-supply options: ST-LINK USB VBUS or external sources _ On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration capability: mass storage, virtual COM port and debug port Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22ARM: DTS: stm32: add stm32h743i-disco filesPatrice Chotard
All these files are imported from linux kernel v4.13 Add device tree support for STM32H743 SoC and discovery board. This board offers : _ STM32H743XIH6 microcontroller with 2 Mbytes of Flash memory and 1 Mbyte of RAM in TFBGA240+25 package _ 5.7” 640x480 TFT color LCD with touch screen _ Ethernet compliant with IEEE-802.3-2002 _ USB OTG HS _ I2 C compatible serial interface _ ST-MEMS digital microphones _ 8-Gbyte (or more) SDIO3.0 interface microSD™ card _ 8Mx32bit SDRAM _ 1-Gbit Twin Quad-SPI NOR Flash _ Reset, wakeup, or key buttons _ Joystick with 4-direction control and selector _ Board connectors : 1 USB with Micro-AB Ethernet RJ45 Stereo headset jack including analog microphone input microSD™ card RCA connector JTAG/SWD and ETM trace _ Expansion connectors: Arduino Uno compatible Connectors 2 x PIO connectors (PMOD and PMOD+) _ On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration capability: mass storage, virtual COM port and debug port Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22ARM: dts: STiH410: update ehci and ohci compatiblePatrice Chotard
Update ehci and ohci node's compatible string in order to use ehci-generic and ohci-generic drivers. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22ARM: dts: STiH410: set DWC3 dual role mode to peripheralPatrice Chotard
On STi 96boards, configure by default the micro USB connector (managed by DWC3 hardware block) in peripheral mode. This will allow to use fastboot feature. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22usb: dwc3: Add dwc3 glue driver support for STiPatrice Chotard
This patch adds the ST glue logic to manage the DWC3 HC on STiH407 SoC family. It configures the internal glue logic and syscfg registers. Part of this code been extracted from kernel.org driver (drivers/usb/dwc3/dwc3-st.c) Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22ARM: dts: stih410-family: Add missing reset_names for mmc1 nodePatrice Chotard
reset-names property is needed to use the reset API for STi sdhci driver. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-21nds32: board: Support SPI driver.rick
Add spi dts node and enable spi dm flash config. Signed-off-by: rick <rick@andestech.com>
2017-09-21nds32: ftmac100 support cache enable.rick
Enable cache and ftmac100 performance can be improved. Signed-off-by: rick <rick@andestech.com>
2017-09-21nds32: bootm: Fix warning of struct tag_serialnr declaredrick
move #include <asm/setup.h> from bootm.c to bootm.h Signed-off-by: rick <rick@andestech.com>
2017-09-20Merge git://www.denx.de/git/u-boot-imxTom Rini
2017-09-20toradex: imx6: Move g_dnl_bind_fixup() into common SPL codeFabio Estevam
Instead of having every board file to add its own g_dnl_bind_fixup() implementation, move it to the common imx6 SPL code. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Łukasz Majewski <lukma@denx.de>
2017-09-18Merge git://git.denx.de/u-boot-rockchipTom Rini
2017-09-18rockchip: ram: rk3399: update reg map for of-platdataKever Yang
After Simon's patch, the dtoc can work with 64bit address, so we need to fix reg number for it. Depend on Simon's patch set: https://patchwork.ozlabs.org/cover/807266/ Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18rockchip: dts: rk3368: reduce the number of nodes seen in TPLPhilipp Tomsich
The RK3368 TPL stage always returns to the BootROM, so it has no need for the eMMC, SD and SPI nodes. This marks those nodes (that should be included in SPL, but not TPL) as 'u-boot,dm-spl'. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-18rockchip: dts: rk3399-puma: replace 'rockchip, vbus-gpio' with fixed regulatorPhilipp Tomsich
On the RK3399-Q7, we need to turn on the on-module USB hub before using the USB host interfaces (only the OTG interface is directly connected to the edge connector). This drops the deprecated 'rockchip,vbus-gpio' property and uses a fixed regulator to turn on the USB hub. References: 26a8b80 "usb: host: xhci-rockchip: use fixed regulator to control vbus" Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-18rk3288: Add Vyasa initial board supportJagan Teki
This patch adds support for Vyasa RK3288 initial board from Amarula Solutions. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18rockchip: rk3399: spl: remove hard-coded addresses for GRF and SGRFPhilipp Tomsich
On the RK3399, we will have either OF_PLATDATA or full OF_CONTROL enabled: this allows the use of syscon to retrieve the addresses of GRF and SGRF (except for the early debug UART setup, which runs so early that the device-model is not initialised). This removes the hard-coded addresses and goes through syscon to retrieve the base-addresses of GRF and SGRF. After that, we use the structure definitions to locate the respective registers. In addition to this, the inclusion of header files is also cleaned up: - all headers are included at the beginning (there was a spurious inclusion of the grf header from within a function) - all #include statements for unused headers are removed - the remaining #include statements are sorted (while keeping common.h included in front) Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-18rockchip: dts: rk3368-lion: add /chosen/tick-timerPhilipp Tomsich
To support bootstage recording, we want to mark our DM timer as the tick-timer; this triggers the support for 'trying harder' to read the timer in the Rockchip DM timer driver, even if the device model isn't ready yet. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18rockchip: rk322x: Disable integrated macphy for saving power consumingDavid Wu
Unfortunately, the integrated macphy default is enabled, which will increase power consuming, if we do not use this PHY. So let's disable it at first, which will save power consuming. If we really use it, then enable it in driver level. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18rockchip: rk322x: enable fastboot to set boot mode tagKever Yang
To support fastboot "fastboot reboot-bootloader" cmd. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18ARM: dts: rockchip: add USB nodes for evb-rv1108William Wu
This patch adds USB OTG/EHCI/OHCI nodes for evb-rv1108 USB ports. Signed-off-by: William Wu <william.wu@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18imx: imx7d: remove CamelCase from ENET_xMHz macrosEric Nelson
Update these macros to use all upper-case to avoid checkpatch warnings: ENET_25MHz, ENET_50MHz, ENET_125MHz, Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-09-18imx_common: detect USB serial downloader reliablyStefan Agner
The current mechanism using SCR/GPR registers work well when the serial downloader boot mode has been selected explicitly (either via boot mode pins or using bmode command). However, in case the system entered boot ROM due to unbootable primary boot devices (e.g. empty eMMC), the SPL fails to detect that it has been downloaded through serial loader and tries to continue booting from eMMC: Trying to boot from MMC1 mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ### The only known way to reliably detect USB serial downloader is by checking the USB PHY receiver block power state... Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com>
2017-09-18Merge git://git.denx.de/u-boot-uniphierTom Rini
2017-09-18imx: add macro to detect whether USB PHY is activeStefan Agner
This macro allows to detect whether the USB PHY is active. This is helpful to detect if the boot ROM has previously started the USB serial downloader. The idea is taken from the mfgtool support in the NXP U-Boot: http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/commit/?h=imx_v2016.03_4.1.15_2.0.0_ga&id=a352ed3c5184b95c4c9f7468f5fbb5f43de5e412 Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com>
2017-09-18ARM: uniphier: add GPU(Mali) reset deassert and clk enableMasahiro Yamada
The driver for Linux is out of control of Socionext, so set up reset / clock in here. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-09-18ARM: uniphier: remove bit field macros from sc64-regs.hMasahiro Yamada
Starting from PXs3, the bit fields of RSTCTRL, CLKCTRL registers will change every SoC. There is no more point to define bitfields in the common header file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-09-18ARM: uniphier: merge two defconfig files into uniphier_v7_defconfigMasahiro Yamada
The main difference between Pro4 and PXs2/LD6b is the Denali NAND IP version. This is now distinguished by DT. Merge the two defconfig files into uniphier_v7_defconfig. Update the README.uniphier too. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-09-16x86: ivybridge: remove unused variablesHeinrich Schuchardt
legacy_hole_base_k and legacy_hole_size_k are defined but not used. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-16dm: x86: Allow TSC timer to be used before DM is readySimon Glass
With bootstage we need access to the timer before driver model is set up. To handle this, put the required state in global_data and provide a new function to set up the device, separate from the driver's probe() method. This will be used by the 'early' timer also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-16x86: Support Intel Cherry Hill boardBin Meng
This adds support to Intel Cherry Hill board, a board based on Intel Braswell SoC. The following devices are validated: - serial port as the serial console - on-board Realtek 8169 ethernet controller - SATA AHCI controller - EMMC/SDHC controller - USB 3.0 xHCI controller - PCIe x1 slot with a graphics card - ICH SPI controller with an 8MB Macronix SPI flash - Integrated graphics device as the video console Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16x86: braswell: Disable PUNIT power configuration for B0 steppingBin Meng
FSP's built-in UPD configuration enables PUNIT power configuration, but on B0 stepping, this causes CPU hangs in fsp_init(). Disable it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16x86: braswell: Add FSP configurationBin Meng
Add FSP related configuration for Braswell. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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