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2020-08-20versal: fix versal PM ret payload sizeIbai Erkiaga
The PM return payload size is defined as 4 bytes for Versal arquitecture while the PM calls implemented both in the Versal clock driver and ZynqMP firmware driver expects 5 bytes length. Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-08-20xilinx: versal: Add new versal loadpdi commandT Karthik Reddy
Versal loadpdi command is used for loading secure & non-secure pdi images. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-08-19dts: r64: add sata- and asm_sel nodesFrank Wunderlich
asm_sel is for switching between sata and pcie mode on r64 there is GPIO90 connected to ASM1480 which switches RX/TX pairs to PCIe/SATA connector output-low means sata-controller is active with 2020-10 now reg is also needed for the phy itself Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2020-08-19arm: dts: mt7622: add PCIe nodes for BananaPi-R64Frank Wunderlich
this patch adds PCIe-Nodes for BananaPi R64 original nodes from Chuanjia Liu for mt7622-rfb Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2020-08-19dts: r64: add r64 dtsFrank Wunderlich
add a separate DTS for BananaPi R64 because it has 1GB RAM and SATA-Support Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2020-08-19arm: dts: add watchdog-node for mt7622Frank Wunderlich
adding a watchdog-node to mt7622 dtsi Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2020-08-19arm: dts: mediatek: add PCIe node for MT7622Chuanjia Liu
This patch adds PCIe node in dts for Mediatek MT7622 Soc. Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com> Signed-off-by: Henry Yen <henry.yen@mediatek.com>
2020-08-19arm: dts: mediatek: add pciesys support for MT7622 SoCChuanjia Liu
This patch adds pciesys support in dts for MediaTek MT7622 SoC. Signed-off-by: Henry Yen <henry.yen@mediatek.com> Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com>
2020-08-18ARM: dts: uniphier: resync DT with Linux 5.9-rc1Masahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-08-18ARM: uniphier: use FIELD_GET() to get access to revision register fieldsMasahiro Yamada
Define register fields as macros, and use FIELD_GET(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-08-18ARM: uniphier: remove unneeded header inclusion from board_late_init.cMasahiro Yamada
<nand.h> is unneeded since commit 9248a78f40d6 ("ARM: UniPhier: remove Denali NAND controller fixup code"). <linux/io.h> is uneeded since commit 1320fa2e55d2 ("ARM: uniphier: remove workaround for the NAND write protect"). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-08-18ARM: uniphier: remove unused uniphier_pin_init()Masahiro Yamada
This function is unused since commit 862274913f8f ("bus: uniphier-system-bus: move hardware init from board files"). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-08-17ARM: imx: ddr: Add deskew register programmingMarek Vasut
Fill is code for programming the DDR_PHY_CMD_DESKEW_CONx registers, which are optional, but can be used to fill in the byte lane delays. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2020-08-17ARM: imx: Add support for reading out the primary/secondary bmode to MX7Marek Vasut
Implement the 'getprisec' subcommand of 'bmode' command for i.MX7 by reading out the SRC GPR10 bit 30. This bit is either set by the BootROM if it switched to the secondary copy due to primary copy being corrupted OR it can be overridden by the user. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
2020-08-17ARM: imx: Add support for reading out the primary/secondary bmodeMarek Vasut
Add new 'getprisec' subcommand to 'bmode' command, which sets the return value of the 'bmode' command to either 0 if the system booted from primary copy or to 1 if the system booted from secondary copy. This can be used e.g. in 'test' command to determine which copy of the system is running. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
2020-08-17ARM: imx: Add support for switching primary/secondary boot mode to bmodeMarek Vasut
The i.MX6/i.MX7 is capable of booting a secondary "redundant" system image in case the primary one is corrupted. The user can force this boot mode as well by explicitly setting SRC GPR10 bit 30. This can be potentially useful when upgrading the bootloader itself. Expose this functionality to the user. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
2020-08-17ARM: imx: Add bmode support for iMX7Marek Vasut
Add the basic differentiation between i.MX6 and i.MX7 into the bmode command, the mechanism really works almost the same on both platforms. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2020-08-14xen: Port Xen bus driver from mini-osOleksandr Andrushchenko
Make required updates to run on u-boot and strip test code. Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com> Signed-off-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
2020-08-14serial: serial_xen: Add Xen PV serial driverPeng Fan
Add support for Xen para-virtualized serial driver. This driver fully supports serial console for the virtual machine. Please note that as the driver is initialized late, so no banner nor memory size is visible. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com> Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-14xen: Port Xen hypervisor related code from mini-osOleksandr Andrushchenko
Port hypervisor related code from Mini-OS. This is referencing the code of Mini-OS from [1] by Huang Shijie and Volodymyr Babchuk which is for ARM64. Update essential arch code to support required bit operations, memory barriers etc. Copyright for the bits ported belong to at least the following authors, please see related files for details: Copyright (c) 2002-2003, K A Fraser Copyright (c) 2005, Grzegorz Milos, gm281@cam.ac.uk,Intel Research Cambridge Copyright (c) 2014, Karim Allah Ahmed <karim.allah.ahmed@gmail.com> [1] - https://github.com/zyzii/mini-os.git Signed-off-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com> Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com> [trini: Drop wmb() from musb-net/linux-compat.h now] Signed-off-by: Tom Rini <trini@konsulko.com>
2020-08-14board: Introduce xenguest_arm64 boardAndrii Anisov
Introduce a minimal Xen guest board running as a virtual machine under Xen Project's hypervisor [1], [2]. Part of the code is ported from Xen mini-os and also uses work initially done by different authors from NXP: please see relevant files for their copyrights. [1] https://xenbits.xen.org [2] https://wiki.xenproject.org/ Signed-off-by: Andrii Anisov <andrii_anisov@epam.com> Signed-off-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com> Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com>
2020-08-14include/configs: aspeed: Remove hardcoded variablesChia-Wei, Wang
The hardcoded platform variables such as DRAM base address are not common to Aspeed SoCs AST24xx/AST25xx/AST26xx. This patch replaces those hardcoded with macros defined in a newly added header, where the basic SoC HW information are assigned accordingly. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2020-08-14cosmetic: aspeed: ast2500: Rename board fileChia-Wei, Wang
Rename the ast2500-board.c to board_common.c and place the renamed file under the ast2500 folder. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2020-08-14aspeed: ast2500: Add lowlevel_init assemblyChia-Wei, Wang
The original lowlevel_init function of AST2500 is written in C. However, the C runtime environment is not ready until _main execution. This patch adds the assembly version of the lowlevel_init function. Additional initialization to DRAM configuration and LPC reset source are also added. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2020-08-14riscv: additional crash informationHeinrich Schuchardt
If an exception occurs, the relocated program counter and return address are required for an analysis. With this patch you get: => exception undefined Unhandled exception: Illegal instruction EPC: 0000000080595908 RA: 000000008059c0c6 TVAL: 000000008030c01e EPC: 0000000080007908 RA: 000000008000e0c6 reloc adjusted We can use the relocated addresses to find the involved functions in u.boot.map: .text.do_undefined 0x0000000080007908 0x8 cmd/built-in.o .text.cmd_process 0x000000008000dfcc 0x11a common/built-in.o 0x000000008000dfcc cmd_process If an exception occurs in an UEFI binary additionally the load addresses of the UEFI binaries are needed. With this patch: => setenv efi_selftest exception => bootefi selftest Unhandled exception: Illegal instruction EPC: 000000008042e18a RA: 000000008042e18a TVAL: 000000008030c01e EPC: 000000007fea018a RA: 000000007fea018a reloc adjusted UEFI image [0x0000000000000000:0xffffffffffffffff] '/\selftest' UEFI image [0x000000008042e000:0x000000008042e43f] pc=0x18a '/bug.efi' The value pc=0x18a matches the position of the illegal instruction in efi_selftest_miniapp_exception.efi (loaded as /bug.efi); asm volatile (".word 0xffffffff\n"); 00000180 93 85 C5 11 1C 64 22 85 82 97 FF FF FF FF 1C 64 Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Sean Anderson <seanga2@gmail.com> Tested-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-08-14riscv: sifive: fu540: redundant initializationHeinrich Schuchardt
We should not initialize a variable if the value is overwritten before being read. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com> Tested-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-08-14riscv: remove redundant logical constraint.Heinrich Schuchardt
After if (ret) return ret; we know that ret is zero. Don't check it again. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-08-14riscv: sifive/fu540: kconfig: Move FU540 driver related options to the SoC levelBin Meng
All FU540 driver related options should be in the SoC level Kconfig. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com> Tested-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-08-14riscv: sifive/fu540: spl: Rename soc_spl_init()Bin Meng
spl_soc_init() seems to be a better name, as all SPL functions names start from the spl_ prefix. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com> Tested-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-08-14riscv: Call spl_board_init_f() in the generic SPL board_init_f()Bin Meng
The generic SPL version of board_init_f() should give a call to board specific codes to initialize board in the SPL phase. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com> Tested-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-08-13Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini
- Fix dtc warnings for some MVEBU boards
2020-08-13Merge tag 'u-boot-stm32-20200813' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - Use IS_ENABLED to prevent ifdef in board_key_check for STM32MP - Add STM32 FMC2 EBI controller driver - Fix dwc3-sti-glue which allows STiH410-B2260 to boot again - Add fitImage its entry for 587-200 DHCOR SoM - Add both PDK2 and DRC02 DT into DHCOM fitImage its - Fix DHCOM KS8851 ethernet MAC address - Remove stm32mp1 board.c file - Use const for struct node_info in board stm32mp1.c file
2020-08-13arm: mvebu: armada-3720-turris-mox.dts: Fix dtc warningStefan Roese
Fix this dtc warning: Warning (avoid_default_addr_size) Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Behún <marek.behun@nic.cz>
2020-08-13arm: mvebu: armada-388-gp.dts: Fix dtc warningsStefan Roese
Fix these dtc warnings: Warning (reg_format) Warning (avoid_default_addr_size) Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chris Packham <judge.packham@gmail.com> Reviewed-by: Chris Packham <judge.packham@gmail.com>
2020-08-13arm: mvebu: armada-xp-maxbcm.dts: Fix dtc warningStefan Roese
Fix this dtc warning: Warning (avoid_default_addr_size) Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-13arm: mvebu: armada-xp-theadorable.dts: Fix dtc warningStefan Roese
Fix this dtc warning: Warning (avoid_default_addr_size) Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-13ARM: dts: stm32: Update eth1addr from EEPROM if eth1 presentMarek Vasut
The STM32MP1 DHCOM has two ethernet interfaces, the on-SoM DWMAC and KS8851. Set eth1addr for the KS8851 to a MAC address of the DWMAC incremented by 1. The MAC of the DWMAC is set from on-SoM EEPROM already, but the MAC address of KS8851 was left uninitialized, so fix this. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-08-13ARM: dts: stm32: add FMC2 EBI support for stm32mp157cChristophe Kerello
This patch adds FMC2 External Bus Interface support on stm32mp157c. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-08-13arm: stm32mp: stm32prog: use IS_ENABLED to prevent ifdefPatrick Delaunay
Use IS_ENABLED to prevent ifdef in stm32prog command. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-08-13arm: stm32mp: bsec: use IS_ENABLED to prevent ifdefPatrick Delaunay
Use IS_ENABLED to prevent ifdef in bsec driver. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-08-11arm: dts: k3-j7200-common-proc-board: Enable CPSW2G portVignesh Raghavendra
Enable CPSW2G port to support networking in U-Boot Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-08-11ARM: dts: k3-j7200-mcu-wakeup: Add CPSW2G supportVignesh Raghavendra
Add MCU NAVSS, UDMA and CPSW2G DT nodes. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-08-11ARM: dts: k3-j7200: Add HyperBus and HyperFlash nodesVignesh Raghavendra
J7200 SoM has Cypress HyperFlash connected to HyperBus interface, add DT entries for the same. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-08-11ARM: dts: k3-j7200: Add wkup gpio nodeVignesh Raghavendra
Add wkup_gpio0 node required for detecting whether board mux is set HyperFlash. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-08-11arm: dts: k3-j7200: Add USB related DT entriesVignesh Raghavendra
Add USB related DT entries to enable USB device mode. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-08-11arm: dts: k3-j7200: Add R5 specific dts supportDave Gerlach
Add the basic a72 basic dts for j7200. Following nodes were supported: - UART - MMC SD - I2C - TISCI communication - LPDDR with 1600MTs configuration. Signed-off-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2020-08-11arm: dts: k3-j7200: Add dts supportLokesh Vutla
Add the basic a72 dts for j7200. Following nodes were supported: - UART - MMC SD - I2C - TISCI communication Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Vishal Mahaveer <vishalm@ti.com> Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11arm: mach-k3: j7200: Detect if ROM has already loaded sysfwLokesh Vutla
Detect if sysfw is already loaded by ROM and pass this information to sysfw loader. Based on this information sysfw loader either loads the sysfw image from boot media or just receives the boot notification message form sysfw. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com>
2020-08-11arm: mach-k3: j7200: Add support for storing extended boot info from ROMLokesh Vutla
Starting J7200 SoC, ROM supports for loading sysfw directly from boot image. ROM passes this information on number of images that are loaded to bootloader at certain location. Add support for storing this information before it gets corrupted. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com>
2020-08-11arm: mach-k3: j7200: Add support for SOC detectionLokesh Vutla
The J7200 SoC is a part of the K3 Multicore SoC architecture platform. It is targeted for automotive gateway, vehicle compute systems, Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications. The SoC aims to meet the complex processing needs of modern embedded products. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, two clusters of lockstep capable dual Cortex-R5F MCUs and a Centralized Device Management and Security Controller (DMSC). * Configurable L3 Cache and IO-coherent architecture with high data throughput capable distributed DMA architecture under NAVSS. * Integrated Ethernet switch supporting up to a total of 4 external ports in addition to legacy Ethernet switch of up to 2 ports. * Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems, 20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C and I2C, eCAP/eQEP, eHRPWM among other peripherals. * One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL management. See J7200 Technical Reference Manual (SPRUIU1, June 2020) for further details: https://www.ti.com/lit/pdf/spruiu1 Add support for detection J7200 SoC Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com>
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