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2013-05-14Merge branch 'master' of git://git.denx.de/u-boot-blackfin into ↵Tom Rini
powerpc-eldk53-warning-fixes
2013-05-13Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini
2013-05-13x86: Add coreboot timestampsSimon Glass
Add selected coreboot timestamps into bootstage to get a unified view of the boot timings. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-05-13x86: Support adding coreboot timestanps to bootstageSimon Glass
Coreboot provides a lot of useful timing information. Provide a facility to add this to bootstage on start-up. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-05-13x86: Re-enable PCAT timer 2 for beepingSimon Glass
While we don't want PCAT timers for timing, we want timer 2 so that we can still make a beep. Re-purpose the PCAT driver for this, and enable it in coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-05-13x86: Remove ISR timerSimon Glass
This is no longer used since we prefer the more accurate TSC timer, so remove the dead code. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Graeme Russ <graeme.russ@gmail.com>
2013-05-13x86: Remove old broken timer implementationSimon Glass
Tidy up some old broken and unneeded implementations. These are not used by coreboot or anything else now. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: Michael Spang <spang@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Acked-by: Graeme Russ <graeme.russ@gmail.com>
2013-05-13x86: Add TSC timerSimon Glass
This timer runs at a rate that can be calculated, well over 100MHz. It is ideal for accurate timing and does not need interrupt servicing. Tidy up some old broken and unneeded implementations at the same time. To provide a consistent view of boot time, we use the same time base as coreboot. Use the base timestamp supplied by coreboot as U-Boot's base time. Signed-off-by: Simon Glass <sjg@chromium.org>base Signed-off-by: Simon Glass <sjg@chromium.org>
2013-05-13x86: Rationalise kernel booting logic and bootstageSimon Glass
The 'Starting linux' message appears twice in the code, but both call through the same place. Unify these and add calls to bootstage to mark the occasion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Michael Spang <spang@chromium.org> Acked-by: Graeme Russ <graeme.russ@gmail.com>
2013-05-13x86: Implement panic output for corebootSimon Glass
panic_puts() can be called in early boot to display a message. It might help with early debugging. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Wai-Hong Tam <waihong@chromium.org>
2013-05-13x86: Declare global_data pointer when it is usedSimon Glass
Several files use the global_data pointer without declaring it. This works because the declaration is currently a NOP. But still it is better to fix this so that x86 lines up with other archs. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-05-13x86: Remove legacy board init codeSimon Glass
Since we use CONFIG_SYS_GENERIC_BOARD on x86, we don't need this anymore. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Graeme Russ <graeme.russ@gmail.com>
2013-05-13x86: Remove unused portion of link scriptSimon Glass
Since we don't have real-mode code now, we can remove this chunk of the link script. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Graeme Russ <graeme.russ@gmail.com>
2013-05-13x86: Remove unused bios/pci codeSimon Glass
Graeme Russ pointed out that this code is no longer used. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Graeme Russ <graeme.russ@gmail.com>
2013-05-13avr32: fix relocation address calculationAndreas Bießmann
Commit 1865286466a5d0c7f2e3c37632da56556c838e9e (Introduce generic link section.h symbol files) changed the __bss_end symbol type from char[] to ulong. This led to wrong relocation parameters which ended up in a not working u-boot. Unfortunately this is not clear to see cause due to RAM aliasing we may get a 'half-working' u-boot then. Fix this by dereferencing the __bss_end symbol where needed. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-05-13bfin: Move gpio support for bf54x and bf60x into the generic driver folder.Sonic Zhang
The gpio spec for bf54x and bf60x differ a lot from the old gpio driver for bf5xx. A lot of machine macros are used to accomodate both code in one gpio driver. This patch split the old gpio driver and move new gpio2 support to the generic gpio driver folder. - To enable gpio2 driver, macro CONFIG_ADI_GPIO2 should be defined in the board's config header file. - The gpio2 driver supports bf54x, bf60x and future ADI processors, while the older gpio driver supports bf50x, bf51x, bf52x, bf53x and bf561. - All blackfin specific gpio function names are replaced by the generic gpio APIs. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2013-05-13blackfin: Add comments for watchdog event initialization.Sonic Zhang
- Add comments for watchdog event initialization. - Make sure the writting operation to MMRs are finished. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2013-05-13blackfin: Move blackfin serial driver out of blackfin arch folder.Sonic Zhang
- Move blackfin serial driver to the generic driver folder. - Move blackfin serial headers to blackfin arch head folder. - Update the include path to blackfin serial header in start up code. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2013-05-13blackfin: Move blackfin watchdog driver out of the blackfin arch folder.Sonic Zhang
- Enable hw_watchdog_init() in watchdog.h if CONFIG_HW_WATCHDOG is defined. - Move blackfin hw watchdog driver to the generic driver folder. - Call hw_watchdog_init() from blackfin board init code. - Reuse macro CONFIG_WATCHDOG_TIMEOUT_MSECS - Update README.watchdog accordingly Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2013-05-13bf609: add SPI register base addressScott Jiang
- BF609 spi driver depend on this. Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2013-05-13blackfin: Uart divisor should be set after their values are generated.Sonic Zhang
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2013-05-13blackfin: Add memory virtual console to blackfin serial driver.Sonic Zhang
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2013-05-13blackfin: Enable early print via the generic serial API.Sonic Zhang
Remove blackfin specific implementation of the generic serial API when early print macro is defined. In BFIN_BOOT_BYPASS mode, don't call generic serial_puts, because early print in bypass mode is running before code binary is relocated to the link address. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2013-05-13blackfin: bf609: add softswitch config commandBob Liu
Add softswitch_output command for bf609-ezkit to enable softswitches. Signed-off-by: Bob Liu <lliubbo@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2013-05-13blackfin: Correct early serial mess output in BYPASS boot mode.Sonic Zhang
The early serial should not be configured again in initcode() for BYPASS boot mode and in start() for the other LDR boot modes. In BYPASS boot mode, the start up code is located in Nor flash address other than the DRAM address defined in link script. The code embedded string can't be addressed by its compile time symbol. Calculate it according to the flash offset. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2013-05-13blackfin: Set correct early debug serial baudrate.Sonic Zhang
Calculate the early uart clock from the system clock registers set by the bootrom other than the predefine uboot clock macros. Split the early baudrate setting function and the normal baudrate setting one. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2013-05-13blackfin: run core1 from L1 code sram start address in uboot init code on core 0Sonic Zhang
Define core 1 L1 code sram start address. Add function to enable core 1 for BF609 and BF561. Add config macro to allow customer to run core 1 in uboot init code on core 0. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2013-05-13blackfin: add baudrate to bdinfoBob Liu
Signed-off-by: Bob Liu <lliubbo@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2013-05-13Blackfin: adjust asm constraints with NMI workaroundMike Frysinger
Newer gcc versions will sometimes use a Preg when "r" constraints, but that'll fail if we use an Ireg in the assignment. So force the code to always use a Dreg. This also fixes early boot crashes for older Blackfin parts when compiled with gcc-4.5. This version ends up selecting the same register for the input and output variables which corrupts the output assignment triggering an exception. P2 = 0xffe02008; /* EVT2 */ R0 = RETS; CALL 1f; RTN; 1: P2 = RETS; <-- BAD RETS = R0; [P2] = P2; <-- BAD Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2013-05-13blackfin: limit the max memory dma peripheral transfer size to 4 bytes.Sonic Zhang
Othersize, the bf609 memory dma halts after being enabled. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2013-05-13blackfin: Change the member's type in dma structures.Sonic Zhang
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2013-05-10openrisc: move board linker script(s) to a common in cpu/Stefan Kristiansson
Unifies the openrisc boards linker scripts into a common one. Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
2013-05-09gpio: Add support for microblaze xilinx GPIOMichal Simek
Microblaze uses gpio which is connected to the system reset. Currently gpio subsystem wasn't used for it. Add gpio driver and change Microblaze reset logic to be done via gpio subsystem. There are various configurations which Microblaze can have that's why gpio_alloc/gpio_alloc_dual(for dual channel) function has been introduced and gpio can be allocated dynamically. Adding several gpios IP is also possible and supported. For listing gpio configuration please use "gpio status" command This patch also remove one compilation warning: microblaze-generic.c: In function 'do_reset': microblaze-generic.c:38:47: warning: operation on '*1073741824u' may be undefined [-Wsequence-point] Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-05-09microblaze: bootm: Add support for loading initrdMichal Simek
fdt_initrd add additional information to DTB about initrd addresses which are later used by kernel. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-05-09microblaze: bootm: Fix coding style issuesMichal Simek
Prepare place for new patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-05-08nds32: Use sections header to obtain link symbolsKuan-Yu Kuo
Include this header to get access to link symbols, which are otherwise removed. Signed-off-by: Kuan-Yu Kuo <ken.kuoky@gmail.com> Cc: Macpaul Lin <macpaul@gmail.com>
2013-05-02Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini
2013-05-02powerpc/mpc85xx: Changed LIODN offset valuesCristian Sovaiala
Extending LIODN offset range from 1-5 to 1-10 While using a qman portal with a higher index the LIODN offset is incorrectly set, thus extending the range of offsets covers all 10 qman portals Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com> Acked-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02powerpc/mpc85xx: Extend workaround for erratum DDR_A003 to other SoCsYork Sun
Erratum DDR_A003 applies to P5020, P3041, P4080, P3060, P2041, P5040. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02powerpc/85xx: add SerDes bank 4 lanesTimur Tabi
Only some chips have four SerDes banks, so don't define lanes for a bank that doesn't exist. Signed-off-by: Timur Tabi <timur@tabi.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02powerpc/mpc85xx:IFC Errata A003399 is not valid for BSC913xPrabhakar Kushwaha
As per Errata list of BSC9131 and BSC9132, IFC Errata A003399 is no more valid. So donot compile its workaround. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02mpc85xx: Fix a compiler warning when CONFIG_WATCHDOG is turned onHorst Kronstorfer
cpu.c:288:2: warning: implicit declaration of function 'reset_85xx_watchdog' [-Wimplicit-function-declaration] Signed-off-by: Horst Kronstorfer <hkronsto@frequentis.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02powerpc/85xx: Add workaround for errata USB-14 (enable on P204x/P3041/P50x0)Xulei
On P204x/P304x/P50x0 Rev1.0, USB transmit will result in false internal multi-bit ECC errors, which has impact on performance, so software should disable all ECC reporting from USB1 and USB2. In formal release document, the errata number should be USB14 instead of USB138. Signed-off-by: xulei <Lei.Xu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: xulei <B33228@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02fman/mEMAC: set SETSP bit in IF_MODE regisgter for RGMII speedZang Roy-R61911
Some legacy RGMII phys don't have in band signaling for the speed information. so set the RGMII MAC mode according to the speed got from PHY. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Reported-by: John Traill <john.traill@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02powerpc/mpc85xx: set clock-frequency for T4/B4 clockgen nodeTang Yuantian
For T4/B4, the clockgen node compatible string is updated to version 2. Add clock-frequency setting for this new version. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02powerpc/b4860: Adding workaround errata A-005871Shengzhou Liu
Per the latest errata updated, B4860/B4420 Rev 1.0 has also errata A-005871, so adding define A-005871 for B4 SoCs. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02powerpc/b4: Fix the wrong register offset of B4 PCIE moduleLiu Gang
B4420/B4860 PCIE can not work because of the wrong definition of the PCIE register offset in the file: arch/powerpc/include/asm/immap_85xx.h Add the judgement of B4420/B4860 to make the register offset to: #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000 Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02powerpc/mpc85xx: add setting of clock-frequency for mpic nodeDongsheng.wang@freescale.com
Set the device tree property associated with the mpic source frequency. The frequency is used for mpic timer. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02powerpc/mpc85xx: Add revision properties in portal device tree node 'pme'Jeffrey Ladouceur
The 'fsl,pme-rev1' and 'fsl-pme-rev2' properties have been added to the pme portal node. This is required for software to determine which version of PME hardware is present and take appropriate actions. These properties are a direct reflection of the corresponding ccsr pme register value. Also removed unnecessary static global variables. Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxxTom Rini
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