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2018-10-09sandbox: Restore blocking I/O on exitSimon Glass
At present sandbox sets non-blocking I/O as soon as any input is read from the terminal. However it does not restore the previous state on exit. Fix this and drop the old os_read_no_block() function. This means that we always enable blocking I/O in sandbox (if input is a terminal) whereas previously it would only happen on the first call to tstc() or getc(). However, the difference is likely not important. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-10-09dm: spi: Clean up detection of sandbox SPI emulatorSimon Glass
Now that we don't have to deal with the command-line flag we can simplify the code for detecting the emulator. Remove the lookup based on the SPI specification, relying just on the device tree to locate the emulator. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-10-09sandbox: Remove the old memory file laterSimon Glass
When debugging sandbox it is sometimes annoying that the memory file is deleted early on. If sandbox later crashes or we quit (using the debugger), it is not possible to run it again with the same state since the memory file is gone. Remove the old memory file when sandbox exits, instead. Also add debugging showing the memory filename. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-10-09sandbox: Add a flag to set the default log levelSimon Glass
It is useful to be able to set the default log level from the command line when running sandbox. Add a new -L command-line flag for this. The log level is set using the enum log_level_t in log.h. At present a number must be specified, e.g. -L7 for debug. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-10-09sandbox: Support booting from TPL to SPLSimon Glass
At present we support booting from SPL to U-Boot proper. Add support for the previous stage too, so sandbox can be started with TPL. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-10-09sandbox: Add a way to write data to the host filesystemSimon Glass
For debugging it is sometimes useful to write out data for inspection using an external tool. Add a function which can write this data to a given file. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-10-09sandbox: Support file truncation with os_open()Simon Glass
At present files are not truncated on writing. This is a useful feature. Add support for this. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-10-08sandbox: Unprotect DATA regions in bus testsSimon Glass
On my Ubuntu 18.04.1 machine two driver-model bus tests have started failing recently. The problem appears to be that the DATA region of the executable is protected. This does not seem correct, but perhaps there is a reason. To work around it, unprotect the regions in these tests before accessing them. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-10-07Kconfig: sandbox: enable cmd_avb and dependenciesJens Wiklander
Enables cmd_avb and its dependencies need to run the AVB tests. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> [trini: Disable for sandbox_noblk] Signed-off-by: Tom Rini <trini@konsulko.com>
2018-10-07sandbox: imply CONFIG_TEE (TEE uclass)Jens Wiklander
Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2018-10-07sandbox: dt: add sandbox_tee nodeJens Wiklander
Adds a sandbox_tee node to enable the sandbox tee driver in all the sandbox dts files. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2018-10-07arm: dt: hikey: Add optee nodeJens Wiklander
Sync with 14e21cb8f811 ("arm64: dt: hikey: Add optee node" from Linux kernel. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2018-10-06mach-stm32: Set MPU SDRAM size to 512MB for STM32F7/H7Patrice Chotard
This allows to boot all STM32F7 and STM32H7 boards independently of the amount of embedded SDRAM. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2018-10-06ARM: DTS: Add Logic PD OMAP35/DM37 SOM-LV and OMAP35 TorpedoAdam Ford
With the device trees doing most of the work of pin-muxing and DM doing much of the peripheral initialization, this creates new defconfig files for each of the Logic PD variants with proper register settings/pin-muxing. Signed-off-by: Adam Ford <aford173@gmail.com> [trini: Update MAINTAINERS entry] Signed-off-by: Tom Rini <trini@konsulko.com>
2018-10-06ARM: DTS: Add support for Logic PD OMAP35 Torpedo & SOM-LVAdam Ford
The baseboards and SOM's are virtually identical to their DM37 counterparts, but OMAP36/37 and OMAP3 have some minor register differences. With the boards being mostly driven by device trees now, this synchronizes their respective device trees with linux-omap for-next branch destined for 4.20 (or whatever the version after 4.19 will be called) Signed-off-by: Adam Ford <aford173@gmail.com>
2018-10-06ARM: DTS: Remove unnecessary u-boot.dtsi options from omap3/36xxAdam Ford
With the introduction of the omap serial driver, the need for some of these U-Boot specific modifications is gone. This cleans up this unnneeded stuff. Signed-off-by: Adam Ford <aford173@gmail.com>
2018-10-06ARM: DTS: LogicPD-SOM-LV & Torpedo: Resync DTS with KernelAdam Ford
The device tree entries are from linux-omap's for-next branch destined to me put into 4.20 (or whatever the version is after 4.19) Signed-off-by: Adam Ford <aford173@gmail.com>
2018-10-05Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
2018-10-05Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini
2018-10-05Merge tag 'rockchip-for-v2018.11-rc2' of git://git.denx.de/u-boot-rockchipTom Rini
Rockchip-focused changes for v2018.11-rc2: - fixes to rkimage for SPL boot via USB - fixes to make_fit_atf.py, incl. entry-point calculation and python3 compatibility - OP-TEE support for ARMv7-based SoCs - fixes to RGMII/GMII selection on the RK3328 Signed-off-by: Tom Rini <trini@konsulko.com>
2018-10-05arc: Add support for IoT development kitAlexey Brodkin
The DesignWare ARC IoT Development Kit is a versatile platform that includes the necessary hardware and software to accelerate software development and debugging of sensor fusion, voice recognition and face detection designs. More information is avaialble here [1] and here [2]. The board is based on real silicon with ARC EM9D-based Data Fusion IP Subsystem. It sports a rich set of I/O including * DW USB OTG * DW MobileStorage (used for micro SD-card) * GPIO * multiple serial interface including DW APB UART * ADC, PWM and eFlash, SRAM and SPI Flash memory * Real-Time Clock (RTC) * Bluetooth module with worldwide regulatory compliance (FCC, IC, CE, ETSI, TELEC) * On-board 9-axis sensor (gyro, accelerometer and compass) Extensible with Arduino, Pmod, mikroBUS connectors and a 2x18 extension header. One of the most interesting features for developers is built-in Digilent USB JTAG probe so only micro-USB cable is needed! [1] https://www.synopsys.com/dw/ipdir.php?ds=arc_iot_development_kit [2] https://www.synopsys.com/dw/doc.php/ds/cc/iot_dev_kit.pdf Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-10-05ARC: Implement print_cpuinfo()Alexey Brodkin
Once we enable DISPLAY_CPUINFO for ARC we'll see ARC core family and version printed on boot. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-10-05ARC: Add model property to boards .dtsAlexey Brodkin
1. This way we sync with Linux kernel where we have model set for all ARC boards for quite some time, see [1] 2. Once we enable DISPLAY_BOARDINFO for ARC this info will be printed on boot givin some extra data-point about the board [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=618a9cd06dd471ac232f5b27325b24d26eba5571 Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-10-05ARC: Don't pre-define CROSS_COMPILEAlexey Brodkin
Even though arc-linux- prefix is used in ARC prebuilt tools and in Buildroot there're other options like Linux distro cross-tools etc where prefix is different so let's not rely on this default. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-10-04rockchip: make_fit_atf: make python3 compatibleMian Yousaf Kaukab
Make script python3 compatible. No functional changes intended. Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-10-04rockchip: make_fit_atf: use elf entry pointMian Yousaf Kaukab
make_fit_atf.py uses physical address of first segment as the entry point to bl31. It is incorrect and causes following abort when bl31_entry() is called: U-Boot SPL board initTrying to boot from MMC1 "Synchronous Abort" handler, esr 0x02000000 elr: 0000000000000000 lr : 00000000ff8c7e8c x 0: 00000000ff8e0000 x 1: 0000000000000000 x 2: 0000000000000000 x 3: 00000000ff8e0180 x 4: 0000000000000000 x 5: 0000000000000000 x 6: 0000000000000030 x 7: 00000000ff8e0188 x 8: 00000000000001e0 x 9: 0000000000000000 x10: 000000000007fcdc x11: 00000000002881b8 x12: 00000000000001a2 x13: 0000000000000198 x14: 000000000007fdcc x15: 00000000002881b8 x16: 00000000003c0724 x17: 00000000003c0718 x18: 000000000007fe80 x19: 00000000ff8e0000 x20: 0000000000200000 x21: 00000000ff8e0000 x22: 0000000000000000 x23: 000000000007fe30 x24: 00000000ff8d1c3c x25: 00000000ff8d5000 x26: 00000000deadbeef x27: 00000000000004a0 x28: 000000000000009c x29: 000000000007fd90 Fix it by using the entry point from the elf header. Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-10-04rockchip: add fit source file for pack itb with op-teeKever Yang
We package U-Boot and OP-TEE into one itb file for SPL, so that we can support OP-TEE in SPL. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-10-04rockchip: make_fit_atf: fix warning unit_address_vs_regKever Yang
Patch fix warning: /builddir/BUILD/u-boot-2018.05-rc2/"arch/arm/mach-rockchip/make_fit_atf.py" \ arch/arm/dts/rk3399-firefly.dtb > u-boot.its ./tools/mkimage -f u-boot.its -E u-boot.itb >/dev/null && cat /dev/null u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/uboot@1 has a unit name, but no reg property u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/atf@1 has a unit name, but no reg property u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/atf@2 has a unit name, but no reg property u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/atf@3 has a unit name, but no reg property u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/fdt@1 has a unit name, but no reg property u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /configurations/config@1 has a unit name, but no reg property make[1]: Leaving directory '/builddir/BUILD/u-boot-2018.05-rc2/builds/firefly-rk3399' Reported-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-10-03Merge tag 'rockchip-for-v2018.11' of git://git.denx.de/u-boot-rockchipTom Rini
Rockchip changes for 2018.11
2018-10-03arm: socfpga: stratix10: add sgmii in phymode setupOoi, Joyce
Additional sgmii phymode is added in socfpga_phymode_setup() along with a minor fix for maximum number of GMACs. Signed-off-by: Ooi, Joyce <joyce.ooi@intel.com>
2018-10-03arm: socfpga: Remove unused function socfpga_emac_manage_reset()Ley Foon Tan
Remove code from the reset manager that is never called. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-10-03ARM: rmobile: Enable PHY framework on Gen3Marek Vasut
Enable PHY framework on Gen3, this is required for USB EHCI PHY support. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-10-03ARM: rmobile: Mark 4-64GiB as DRAM on Gen3Marek Vasut
Mark area 0x1_0000_0000 - 0x10_0000_0000 as DRAM on Gen3 as the chip is capable of addressing that and U-Boot can make use of it. This patch prevents exception when accessing those areas. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-10-03ARM: dts: rmobile: Reinstate missing i2c6 on PorterMarek Vasut
The I2C6 is used to communicate with the PMIC and it was removed during DT sync with Linux 4.17. Reinstate it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-10-03riscv: allow native compilationHeinrich Schuchardt
If environment variable CROSS_COMPILE is not set, this indicates native compilation. In this case we should not set an arbitrary value which is not applicable for 64bit anyway. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2018-10-03riscv: cosmetic: Reword do_reset() printf message.Rick Chen
The Sentence "reset unsupported yet" is not grammatically correct and should say "reset not supported yet" instead. Suggested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Signed-off-by: Rick Chen <rick@andestech.com>
2018-10-03riscv: Move do_reset() to a common placeBin Meng
We don't have a reset method on any RISC-V board yet. Instead of adding the same 'unsupported' message for each CPU variant it might make more sense to add a generic do_reset function for all CPU variants to lib/, similar to the one for ARM (arch/arm/lib/reset.c). Suggested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03riscv: Add QEMU virt board supportBin Meng
This adds QEMU RISC-V 'virt' board target support, with the hope of helping people easily test U-Boot on RISC-V. The QEMU virt machine models a generic RISC-V virtual machine with support for the VirtIO standard networking and block storage devices. It has CLINT, PLIC, 16550A UART devices in addition to VirtIO and it also uses device-tree to pass configuration information to guest software. It implements RISC-V privileged architecture spec v1.10. Both 32-bit and 64-bit builds are supported. Support is pretty much preliminary, only booting to U-Boot shell with the UART driver on a single core. Booting Linux is not supported yet. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03riscv: kconfig: Imply DM support for some common driversBin Meng
This implies DM support for some common drivers that are used on RISC-V. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03riscv: kconfig: Select DM and OF_CONTROLBin Meng
RISC-V is a pretty new architecture and should support DM and OF_CONTROL by default. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03riscv: ae350: Clean up mixed tabs and spaces in the dtsBin Meng
There are quite a lot of mixed tabs and spaces in the ae350.dts. Clean them up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03riscv: Make start.S available for all targetsBin Meng
Currently start.S is inside arch/riscv/cpu/ax25/, but it can be common for all RISC-V targets. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03riscv: bootm: Pass mhartid CSR value to kernelBin Meng
So far this is hardcoded to zero, and we should read the value from mhartid CSR and pass it to Linux kernel. Suggested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
2018-10-03riscv: Remove CSR read/write defines in encoding.hBin Meng
There is no reason to keep two versions of CSR read/write defines in encoding.h. We already have one set of defines in csr.h, which is from Linux kernel, and let's drop the one in encoding.h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
2018-10-03riscv: Add a helper routine to print CPU informationBin Meng
This adds a helper routine to print CPU information. Currently it prints all the instruction set extensions that the processor core supports. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03riscv: Explicitly pass -march and -mabi to the compilerBin Meng
At present the compiler flag against which architecture and abi variant the riscv image is built for is not explicitly indicated which means the default compiler configuration is used. But this does not work if we want to build a different target (eg: 32-bit riscv images using a toolchain configured for 64-bit riscv). Fix this by explicitly passing -march and -mabi to the compiler. Since generically we don't use floating point in U-Boot, specify the RV[32|64]IMA ISA and software floating ABI. This also fix some alignment coding style issues. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03riscv: Fix coding style issues in the linker scriptBin Meng
There are several coding style issues in the linker script. Fix them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03riscv: Move the linker script to the CPU root directoryBin Meng
The linker script can be shared by all RISC-V targets. Move it to a common place. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03riscv: Remove mach typeBin Meng
Since the mach_id is not used by RISC-V, remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03riscv: bootm: Correct the 1st kernel argument to hart idBin Meng
The first argument of Linux kernel is the risc-v core hart id, from which the kernel is booted from. It is not the mach_id, which seems to be copied from arm. While we are here, this also changes the Linux kernel entry parameters' type to support both 32-bit and 64-bit. Note the hart id is hardcoded to zero for now, and we should change to fill in it with the value read from mhartid CSR of the hart which this routine is currently running on. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
generated by cgit (git 2.34.1) at 2024-12-24 17:26:14 +0000