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To avoid the duplicated code, add the UTMI PLL handle functions,
and add PMC_USB init function too.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
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Due to introducing the new peripheral clock handle functions,
use these functions to clean up the duplicated code.
Meanwhile, remove unneeded header file include, at91_pmc.h.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
[fixup for arm920t code]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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To reduce the duplicated code, add a new file to accommodate
the peripheral's and system's clock handle code, shared with
the SoCs with different ARM core.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
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Remove unnecessary #ifdef CPU_HAS_PCR.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
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This allows U-Boot to expose UMS and DFU protocols on this port in device
mode, or to act as a USB host on the port, using an "OTG" (micro-B to
female A host) cable.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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This new feature causes a Kconfig warning on boards without a display
enabled. Fix this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Remove the old PWM code. Remove calls to CONFIG_LCD functions now that we
are using driver model for video.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Use the driver-model PWM driver in preference to the old code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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There is no need to have these in a separate file as they are not
referenced from anywhere else.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Move this driver over to use driver model. This involves rearranging the
code somewhat. The effect is that everything is run from the probe() method.
Boards which use this are fixed up, but only seaboard is tested.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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We have a structure for the display panel and another for the controller.
There is some overlap between them. Merge them to simplify the driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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At present we have code in arch/arm and code in drivers/video. Move it all
into drivers/video since it is a display driver and our current approach is
to put all driver code in drivers/.
Make a few functions static now that they are not used outside the file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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This file has changed quite a bit since it was set up. Sync it back with
Linux v4.4. Adjust the users slightly to cope with the changes:
- the host1x node is now called host1x@50000000
- we need a clocks node to provide the clk32k_in phandle
- active usb nodes need status = "okay"
- active i2c nodes need status = "okay"
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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This option refers only to the tegra20 video driver, so name it as such
to avoid confusion with tegra124.
Also move this option to Kconfig.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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While we transition to using driver model for video, we need to support both
options.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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We can skip this manual init when using driver model for the PWM.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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There isn't a lot of benefit of have two separate files. With driver model
the code needs to be in the same driver, so it's better to have it in the
same file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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This PWM supports four channels. The driver always uses the 32KHz clock,
and adjusts the duty cycle accordingly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Sync up these files with Linux v4.4. Some differences remain, principally
that the addresses are still 32-bit in U-Boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Sync up these files with Linux v4.4.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Signed-off-by: David Müller <d.mueller@elsoft.ch>
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Signed-off-by: David Müller <d.mueller@elsoft.ch>
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Signed-off-by: David Müller <d.mueller@elsoft.ch>
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Initial commit for PH1-Pro4 Ace and Sanji boards.
Note:
There are two variants for the Ace board in terms of the amount of
DDR memory; 1GB or 2GB.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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This is used for on-board inter-connection.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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This board has an EEPROM connected to the I2C channel 0 of the SoC.
Its slave address is 0x54.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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It turned out that DDR channel 2 was not working on ProXstream2
Vodka board. Add the missing ACBLDR0 register setting to adjust
the delay between the clock lines and the address/command lines.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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If CONFIG_CMD_DDRMPHY_DUMP is enabled, the build fails.
Fixes: 93d92d46cd01 ("ARM: uniphier: add dump command for DDR Multi PHY registers")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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The U-Boot proper building needs to descend arch/arm/mach-uniphier/dram
to build these commands.
Fixes: 93d92d46cd01 ("ARM: uniphier: add dump command for DDR Multi PHY registers")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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This header is no longer used.
This is the last file in arch/arm/mach-uniphier/include/mach/.
At last, I've succeeded in eliminating the mach directory.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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These pin mux settings are cared by the pinctrl drivers.
Remove the ad-hoc code.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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The UniPhier EHCI driver (drivers/usb/host/ehci-uniphier.c) does
nothing special but set the base address and handle reset/clock.
Since commit 4feefdcfe916 ("usb: add clock support for generic EHCI"),
the generic one (drivers/usb/host/ehci-generic.c) can do those, too.
We no longer need to stick to the dedicated driver.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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This allows the EHCI driver to get clocks from device tree.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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This block provides clock and reset control for MIO (Media I/O)
hardware blocks such as USB2.0, SD card, eMMC, etc.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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This block provides clock and reset control for peripherals such as
UART, I2C, IC card, etc.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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These are mainly used for controlling clocks and resets.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Add master clock nodes generated by crystal oscillators.
PH1-sLD3, PH1-LD4: 24.576 MHz
PH1-Pro4, ProXstream2: 25.000 MHz
PH1-Pro5: 20.000 MHz
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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This is the initial commit for the UniPhier clock drivers.
Currently, only the Media I/O clock is supported.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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The USB boot code is too fat and complicated to be included in SPL
(at least for now). So, it was implemented as a separate project
(what we call USB-loader).
The expected boot sequence is as follows:
Boot ROM -> USB-loader -> SPL -> U-Boot proper
The USB-loader loads the SPL and U-Boot proper from a USB memory
onto the locked L2 cache. Then, SPL needs to copy the U-Boot proper
to DRAM, so this mode looks like a NOR boot from the view of SPL.
However, we want to distinguish between (genuine) NOR boot and USB
boot in some places.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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This function is for local use in the file.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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UniPhier SoCs are not equipped with dedicated on-chip SRAM. Instead,
locked outer cache is used as RAM area during the early boot stage
where DRAM is not ready yet. This effectively means MMU must be
always enabled while we are in SPL.
Currently, the SPL image for UniPhier SoCs contains the page table
statically defined at compile time. It has been a burden because the
16KB page table occupies a quarter memory footprint of the 64KB SPL
image.
Finally, there is no more room to implement new features in SPL.
Setting aside the NOR boot mode, this issue can be solved by creating
the page table onto RAM at run time.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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No special reason for the current stack address 0x0ff08000.
Change it to 0x00100000 to simplify the init_page_table.
There are two types of SoCs in terms of the load address of SPL.
[1] PH1-sLD3, PH1-LD4, PH1-sLD8
SPL is loaded at 0x00040000-0x0004ffff
[2] PH1-Pro4, PH1-Pro5, ProXstream2, PH1-LD6b
SPL is loaded at 0x00100000-0x0010ffff
The new stack area (0x000f8000-0x00100000) should be safe for all the
cases.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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This enum is referenced from common/spl/spl.c.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Some of PH1-Pro4 boards are equipped with larger amount of DRAM than
the reference board. Add UMC settings to support them.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Add nand driver support for zynqmp. The Nand
controller used in ZynqMP is Arasan Nand Flash
controller.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
[scottwood: Fix checkpatch warning]
Signed-off-by: Scott Wood <oss@buserror.net>
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Enable this option on all tegra boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
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Signed-off-by: David Müller <d.mueller@elsoft.ch>
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Add keystone net DT support for k2g evm.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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