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2019-04-12ARM: kirkwood: rename KW_CPU_WIN_BASE to MVEBU_CPU_WIN_BASEChris Packham
This will allow the kirkwood platforms to use more common code with the other mvebu SoCs. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12arm: mvebu: x530: Enable watchdog in SPL and U-BootChris Packham
Enable the hardware watchdog to guard against system lock ups when running in the SPL or U-Boot. Stop the watchdog just before booting so that the OS can re-enable it if needed. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12arm: sync armada-xp dts files from Linux 5.0Chris Packham
Bring in the Armada 370/XP dts/dtsi files from Linux. As U-Boot hasn't got the new NAND driver the updating binding has not been included. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-11Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
- Various rmobile fixes
2019-04-09ARM: dts: rmobile: Enable USB on E2 AltMarek Vasut
The E2 Alt board has two USB ports, add missing DT nodes to make the USB available. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09ARM: dts: rmobile: Synchronize Gen3 DTs with Linux 5.0Marek Vasut
Synchronize R-Car Gen3 device trees with Linux 5.0, commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09ARM: dts: rmobile: Synchronize Gen2 DTs with Linux 5.0Marek Vasut
Synchronize R-Car Gen2 device trees with Linux 5.0, commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09ARM: dts: rmobile: Import R8A77965 M3NULCB DTsMarek Vasut
Import R8A77965 M3N ULCB device trees from Linux 5.0 , commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09pinctrl: renesas: Add R8A77965 pin control tablesMarek Vasut
Add pin control tables for R8A77965 from Linux 5.0 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09clk: renesas: Add R8A77965 clock tablesMarek Vasut
Add clock tables for R8A77965 from Linux 5.0 , except for the crit, R and Z clock, which are neither used nor supported by the U-Boot clock framework yet. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09ARM: rmobile: Add dedicated R8A77965 SoC supportMarek Vasut
Add dedicated entry for R8A77965 M3N SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09ARM: rmobile: Enable multi-DTB fit LZO compressionMarek Vasut
Enable LZO compression of the multi-DTB fitImages, since the U-Boot with multiple DTs enabled is becoming quite large and the DTs can be well compressed. The LZO compression saves almost 200 kiB on the Salvator-X(S) and ULCB targets. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09ARM: renesas: Save boot parameters passed in by ATFMarek Vasut
The ATF can pass additional information via the first four registers, x0...x3. The R-Car Gen3 with mainline ATF, register x1 contains pointer to a device tree with platform information. Save these registers for future use. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09Merge tag 'u-boot-atmel-2019.07-a' of git://git.denx.de/u-boot-atmelTom Rini
First set of u-boot-atmel features and fixes for 2019.07 cycle
2019-04-09arm: at91: Add gardena-gateway-at91sam supportStefan Roese
The GARDENA smart Gateway boards are equipped with an Atmel / Microchip AT91SAM9G25 SoC and with 128 MiB of RAM and 256 MiB of NAND storage. This patch adds support for this board including SPL support. Therefore the AT91Boostrap is not needed on this platform any more. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2019-04-09arm: at91: at91sam9x5.dtsi: Add watchdog handleStefan Roese
This makes it possible to reference the watchdog DT node via "&watchdog" from board dts files. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2019-04-09arm: at91: arm926ejs/u-boot-spl.lds: Add _image_binary_end to SPL ldsStefan Roese
This patch adds _image_binary_end to the SPL linker script. This will be used be the upcoming GARDENA AT91SAM based platform, which uses DT in SPL and configures CONFIGURE_SPL_SEPARATE_BSS. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2019-04-09arm: at91: Enable watchdog supportStefan Roese
This patch enables and starts the watchdog on the AT91 platform if configured. The WD timeout value is read in the AT91 WD device driver from the DT, using the "timeout-sec" DT property. If not provided in the DT, the default value of 2 seconds is used. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com>
2019-04-09arm: at91: spl_at91.c: Call spl_early_init() if OF_CONTROL is enabledStefan Roese
This patch adds a call to spl_early_init() to board_init_f() which is needed when CONFIG_SPL_OF_CONTROL is configured. This is necessary for the early SPL setup including the DTB setup for later usage. Please note that this call might also be needed for non SPL_OF_CONTROL board, like the smartweb target. But smartweb fails to build with this call because its binary grows too big. So I disabled it for these kind of targets for now. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Heiko Schocher <hs@denx.de> Tested on the taurus board: Tested-by: Heiko Schocher <hs@denx.de>
2019-04-09arm: at91: Makefile: Compile lowlevel_init only when really necessaryStefan Roese
Make sure that lowlevel_init is not compiled when CONFIG_SKIP_LOWLEVEL_INIT_ONLY is configured. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Heiko Schocher <hs@denx.de> Tested on the taurus board: Tested-by: Heiko Schocher <hs@denx.de>
2019-04-09board: pm9g45: Migrate to CONFIG_DMIlko Iliev
Migrate the following options to CONFIG_DM: CONFIG_DM_GPIO CONFIG_DM_MMC CONFIG_DM_ETH CONFIG_DM_SERIAL CONFIG_DM_USB Signed-off-by: Ilko Iliev <iliev@ronetix.at>
2019-04-09ARM: at91: sama5d2: Wrap cpu detection to fix macb driverAlexander Dahl
When introducing the SAMA5D27 SoCs, the SAMA5D2 series got an additional chip id. The check if the cpu is sama5d2 was changed from a preprocessor definition (inlining a call to 'get_chip_id()') to a C function, probably to not call get_chip_id twice? That however broke a check in the macb ethernet driver. That driver is more generic and also used for other platforms. I suppose this solution was implemented to use it in 'gem_is_gigabit_capable()', without having to stricly depend on the at91 platform: #ifndef cpu_is_sama5d2 #define cpu_is_sama5d2() 0 #endif That only works as long as cpu_is_sama5d2 is a preprocessor definition. (The same is still true for sama5d4 by the way.) So this is a straight forward fix for the workaround. The not working check on the SAMA5D2 CPU lead to an issue on a custom board with a LAN8720A ethernet phy connected to the SoC: => dhcp ethernet@f8008000: PHY present at 1 ethernet@f8008000: Starting autonegotiation... ethernet@f8008000: Autonegotiation complete ethernet@f8008000: link up, 1000Mbps full-duplex (lpa: 0xffff) BOOTP broadcast 1 BOOTP broadcast 2 BOOTP broadcast 3 BOOTP broadcast 4 BOOTP broadcast 5 BOOTP broadcast 6 BOOTP broadcast 7 BOOTP broadcast 8 BOOTP broadcast 9 BOOTP broadcast 10 BOOTP broadcast 11 BOOTP broadcast 12 BOOTP broadcast 13 BOOTP broadcast 14 BOOTP broadcast 15 BOOTP broadcast 16 BOOTP broadcast 17 Retry time exceeded; starting again Notice the wrong reported link speed, although both SoC and phy only support 100 MBit/s! The real issue on reliably detecting the features of that cadence ethernet mac IP block, is probably more complicated, though. Fixes: 245cbc583d ("ARM: at91: Get the Chip ID of SAMA5D2 SiP") Signed-off-by: Alexander Dahl <ada@thorsis.com>
2019-04-08Merge git://git.denx.de/u-boot-riscvTom Rini
- RISC-V arch support SMP. - Support Andestech's PLIC and PLMT. - qemu, fu54e, ae350 boards enable SMP by default. - Fix CONFIG_DEFAULT_DEVICE_TREE failure.
2019-04-08arm: sunxi: Enable DM_MMC on required SoCsJagan Teki
Enabling DM_MMC is forcing CONFIG_BLK=y so if any board which uses SCSI must need to enable DM_SCSI otherwise SCSI reads on that particular target making invalid reading to the disk drive. Allwinner platform do support SCSI on A10, A20 and R40 SoC's out of these only A10 have DM_SCSI enabled. So enabling DM_MMC on A20, R40 would eventually end-up with scsi disk read failures like [1] So, enable DM_MMC in all places of respective SoC's instead of enabling them globally to Allwinner platform. Now, DM_MMC is enabled in Allwinner SoC's except A20 and R40. [1] https://lists.denx.de/pipermail/u-boot/2019-April/364057.html Reported-by: Pablo Sebastián Greco <pgreco@centosproject.org> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-08Merge tag 'fixes-for-2019.04-rc4' of git://git.denx.de/u-boot-stagingTom Rini
- i.MX8QXP-MEK ethernet fix
2019-04-08dts: imx8qxp-mek: Add PHY post reset delayAndrejs Cainikovs
PHY cannot be detected unless we wait about 150 ms. Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@netmodule.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-08watchdog: Move watchdog_dev to data section (BSS may not be cleared)Stefan Roese
This patch moves all instances of static "watchdog_dev" declarations to the "data" section. This may be needed, as the BSS may not be cleared in the early U-Boot phase, where watchdog_reset() is already beeing called. This may result in incorrect pointer access, as the check to "!watchdog_dev" in watchdog_reset() may not be true and the function may continue to run. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: "Marek Behún" <marek.behun@nic.cz> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Tested-by: Michal Simek <michal.simek@xilinx.com> (on zcu100) Reviewed-by: Michal Simek <michal.simek@xilinx.com>
2019-04-08riscv: dts: fix CONFIG_DEFAULT_DEVICE_TREE failureRick Chen
It occurs since commit 27cb7300ffda ("Ensure device tree DTS is compiled"). More details can refer to 89c2b5c02049aea746b1edee0b4e1d8519dec2f4 ARM: fix arch/arm/dts/Makefile Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-08riscv: dts: ae350 support SMPRick Chen
Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-08riscv: ax25: Andes specific cache shall only support in M-modeRick Chen
Limit the cache configuration only can be supported in M mode. It can not be manipulated in S mode. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-08riscv: ax25: Add platform-specific Kconfig optionsRick Chen
Add ax25 RISC-V platform-specific Kconfig options, to include CPU and timer drivers. Also disable ATCPIT100 SoC timer and replace by PLMT. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-08riscv: Add a SYSCON driver for Andestech's PLMTRick Chen
The platform-Level Machine Timer (PLMT) block holds memory-mapped mtime register associated with timer tick. This driver implements the riscv_get_time() which is required by the generic RISC-V timer driver. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-08riscv: Add a SYSCON driver for Andestech's PLICRick Chen
The Platform-Level Interrupt Controller (PLIC) block holds memory-mapped claim and pending registers associated with software interrupt. It is required for handling IPI. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-08riscv: hang if relocation of secondary harts failsLukas Auer
Print an error message and hang if smp_call_function() returns an error, indicating that relocation of the secondary harts has failed. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-04-08riscv: do not rely on hart ID passed by previous boot stageLukas Auer
RISC-V U-Boot expects the hart ID to be passed to it via register a0 by the previous boot stage. Machine mode firmware such as BBL and OpenSBI do this when starting their payload (U-Boot) in supervisor mode. If U-Boot is running in machine mode, this task must be handled by the boot ROM. Explicitly populate register a0 with the hart ID from the mhartid CSR to avoid possible problems on RISC-V processors with a boot ROM that does not handle this task. Suggested-by: Rick Chen <rick@andestech.com> Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Tested-by: Rick Chen <rick@andestech.com>
2019-04-08riscv: boot images passed to bootm on all hartsLukas Auer
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-08riscv: add support for multi-hart systemsLukas Auer
On RISC-V, all harts boot independently. To be able to run on a multi-hart system, U-Boot must be extended with the functionality to manage all harts in the system. All harts entering U-Boot are registered in the available_harts mask stored in global data. A hart lottery system as used in the Linux kernel selects the hart U-Boot runs on. All other harts are halted. U-Boot can delegate functions to them using smp_call_function(). Every hart has a valid pointer to the global data structure and a 8KiB stack by default. The stack size is set with CONFIG_STACK_SIZE_SHIFT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-08riscv: save hart ID in register tp instead of s0Lukas Auer
The hart ID passed by the previous boot stage is currently stored in register s0. If we divert the control flow inside a function, which is required as part of multi-hart support, the function epilog may not be called, clobbering register s0. Save the hart ID in the unallocatable register tp instead to protect the hart ID. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-04-08riscv: delay initialization of caches and debug UARTLukas Auer
Move the initialization of the caches and the debug UART until after board_init_f_init_reserve. This is in preparation for SMP support, where code prior to this point will be executed by all harts. This ensures that initialization will only be performed once on the main hart running U-Boot. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-08riscv: implement IPI platform functions using SBILukas Auer
The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-08riscv: import the supervisor binary interface header fileLukas Auer
Import the supervisor binary interface (SBI) header file from Linux (arch/riscv/include/asm/sbi.h). The last change to it was in commit 6d60b6ee0c97 ("RISC-V: Device, timer, IRQs, and the SBI"). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2019-04-08riscv: add infrastructure for calling functions on other hartsLukas Auer
Harts on RISC-V boot independently, U-Boot is responsible for managing them. Functions are called on other harts with smp_call_function(), which sends inter-processor interrupts (IPIs) to all other available harts. Available harts are those marked as available in the device tree and present in the available_harts mask stored in global data. The available_harts mask is used to register all harts that have entered U-Boot. Functions are specified with their address and two function arguments (argument 2 and 3). The first function argument is always the hart ID of the hart calling the function. On the other harts, the IPI interrupt handler handle_ipi() must be called on software interrupts to handle the request and call the specified function. Functions are stored in the ipi_data data structure. Every hart has its own data structure in global data. While this is not required at the moment (all harts are expected to boot Linux), this does allow future expansion, where other harts may be used for monitoring or other tasks. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-05Merge tag 'u-boot-imx-20190405' of git://git.denx.de/u-boot-imxTom Rini
Fixes for 2019.04 - fix bashism for MX8 - fix ethernet for MX53 - fix docs for i.MX8
2019-04-02DTS: Fix ETH PHY reset on HSC|DDC boards (imx53)Lukasz Majewski
After the commit: "eth: dm: fec: Add gpio phy reset binding" SHA1: efd0b791069af93e9d439a70d1fe2ae8994dbbfa The FEC ETH driver switched to PHY GPIO reset performed with data defined in DTS. For the HSC|DDC boards the GPIO reset signal is active low and hence the wrong DTS description must be changed (otherwise the reset for ETH is not properly setup). Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-04-01Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
Minor fixes for the Alt board and PHY use on Gen2.
2019-03-30ARM: dts: rmobile: Activate I2C7 on AltMarek Vasut
Activate I2C7 on Alt to allow access to the PMIC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-29Revert "rockchip: Drop call to rockchip_dnl_mode_check() for now"Philipp Tomsich
Due to a final resolution not coming up in time for 2019.04 and following the consensus on the discussion, we'll keep this around for 2019.04 after all. This reverts commit 0d968ceb1ff63b0d220a571f438f0d5fe6350e88.
2019-03-26Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
- Various fixes for bugs found by u-boot test.py
2019-03-25Convert CONFIG_ENV_SPI_* to KconfigPatrick Delaunay
This converts the following to Kconfig: CONFIG_ENV_SPI_BUS CONFIG_ENV_SPI_CS CONFIG_ENV_SPI_MAX_HZ CONFIG_ENV_SPI_MODE Most of time these value are not needed, CONFIG_SF_DEFAULT with same value is used, so I introduced CONFIG_USE_ENV_SPI_* to force the associated value for the environment. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-03-25exynos: replace CONFIG_ENV_SPI_BASE by CONFIG_SYS_SPI_BASEPatrick Delaunay
Replace CONFIG_ENV_SPI_BASE by the better CONFIG_SYS_SPI_BASE (it is not the location for environment but the location for U-Boot) and, as it is the only platform with use this define, remove it from whitelist. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
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