summaryrefslogtreecommitdiff
path: root/arch
AgeCommit message (Collapse)Author
2018-12-04move data structure out of cpu.hYork Sun
Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-12-03Merge tag 'xilinx-for-v2019.01' of git://git.denx.de/u-boot-microblazeTom Rini
Xilinx changes for v2019.01 microblaze: - Use default functions for memory decoding - Showing model from DT zynq: - Fix spi flash DTs - Fix zynq_help_text with CONFIG_SYS_LONGHELP - Tune cse/mini configurations - Enabling cse/mini testing with current targets zynqmp: - Enable gzip SPL support - Fix chip detection logic - Tune mini configurations - DT fixes(spi-flash, models, clocks, etc) - Add support for OF_SEPARATE configurations - Enabling mini testing with current targets - Add mini mtest configuration - Some minor config setting nand: - arasan: Add subpage configuration net: - gem: Add 64bit DMA support
2018-12-03Merge tag 'signed-efi-next' of git://github.com/agraf/u-bootTom Rini
Patch queue for efi - 2018-12-03 This release is fully packed with lots of glorious improvements in UEFI land again! - Make PE images more standards compliant - Improve sandbox support - Improve correctness - Fix RISC-V execution on virt model - Honor board defined top of ram (fixes a few boards) - Imply DM USB access when distro boot is available - Code cleanups
2018-12-03Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
- MMC fixes for R-Car Gen3
2018-12-03board: MCR3000: migrate to DM_SERIALChristophe Leroy
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2018-12-03board: MCR3000: use new DM watchdogChristophe Leroy
This patch switches MCR3000 board to the new DM watchdog. The change in u-boot.lds is because MCR3000.o grows a bit with this patch and doesn't fit anymore below env_offset on some versions of GCC. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2018-12-03board: MCR3000: Activate CONFIG_DM and CONFIG_OF_CONTROLChristophe Leroy
Add mcr3000 device tree and activate CONFIG_DM and CONFIG_OF_CONTROL Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2018-12-03powerpc, mpc8xx: clear top of stackChristophe Leroy
Reported-by: Joakim Tjernlund <Joakim.Tjernlund@infinera.com> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Reviewed-by: Joakim Tjernlund <Joakim.Tjernlund@infinera.com>
2018-12-03arm: baltos: move the board to CONFIG_BLKYegor Yefremov
Use DM for both MMC and USB subsystems and use dedicated DTS for U-Boot configuration. Disable SPL support for GPIO and remove EVMSK leftover for DDR power control via GPIO. Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-12-03Merge tag 'u-boot-amlogic-20181203' of git://git.denx.de/u-boot-amlogicTom Rini
ARM: meson: Add regmap support for clock driver and sync DT with 4.19
2018-12-03ARM: meson: Add regmap support for clock driverLoic Devulder
This patch modifies the meson clock driver to use syscon/regmap like the Linux kernel does, as it is needed if we want to share the same DTS files. DTS files are synchronized from Linux 4.19. Signed-off-by: Loic Devulder <ldevulder@suse.de> Acked-by: Neil Armstrong <narmstrong@baylibre.com>
2018-12-03ARM: dts: rmobile: Enable HS400 on Salvator-X, ULCB, EbisuMarek Vasut
Enable the HS400 support in DT on H3, M3W, M3N Salvator-X(S) and ULCB boards as well as E3 Ebisu board. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-12-03ARM: dts: rmobile: Enable SDR modes on E3 EbisuMarek Vasut
Add regulators and pinmuxes for SDHI0 and SDHI1 SD and microSD slots on E3 Ebisu and mark them as capable of up to SDR104 mode of operation. With the SDHI fixes in place, it is now possible to use SDR104. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-12-03ARM: dts: rmobile: Enable SDR104 on Salvator-X and ULCBMarek Vasut
Enable SDR104 modes on M3W and H3 boards. With the SDHI fixes in place, it is now possible to use SDR104. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-12-03ARM: dts: rmobile: Add eMMC DS pinmuxMarek Vasut
Add pinmux entry for the eMMC DS line, as it is connected on these boards. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-12-03ARC: Improve identification of ARC coresAlexey Brodkin
1. Try to guess a ARC core template that was used i.e. not just name a core family but something more menaingful like "ARC HS38", "ARC EM11D" etc. We do it checking availability of the key differentiation features like: - Caches (we actually only check for L1 I$ fpr simplicity) - XY-memory - DSP extensions etc. 2. Identify ARC subsystems 3. Print core clock frequency Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-12-02efi_loader: PSCI reset and shutdownHeinrich Schuchardt
When an operating system started via bootefi tries to reset or power off this is done by calling the EFI runtime ResetSystem(). On most ARMv8 system the actual reset relies on PSCI. Depending on whether the PSCI firmware resides the hypervisor (EL2) or in the secure monitor (EL3) either an HVC or an SMC command has to be issued. The current implementation always uses SMC. This results in crashes on systems where the PSCI firmware is implemented in the hypervisor, e.g. qemu-arm64_defconfig. The logic to decide which call is needed based on the device tree is already implemented in the PSCI firmware driver. During the EFI runtime the device driver model is not available. But we can minimize code duplication by merging the EFI runtime reset and poweroff code with the PSCI firmware driver. As the same HVC/SMC problem is also evident for the ARMv8 do_poweroff and reset_misc routines let's move them into the same code module. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2018-12-02riscv: efi: Generate Microsoft PE format compliant imagesBin Meng
Per Microsoft PE Format documentation [1], PointerToSymbolTable and NumberOfSymbols should be zero for an image in the COFF file header. Currently the COFF file header is hardcoded on RISC-V and these two members are not zero. This updates the hardcoded structure to clear these two members, as well as setting the flag IMAGE_FILE_LOCAL_SYMS_STRIPPED so that we can generate compliant *.efi images. [1] https://docs.microsoft.com/zh-cn/windows/desktop/Debug/pe-format Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2018-12-02arm: efi: Generate Microsoft PE format compliant imagesBin Meng
Per Microsoft PE Format documentation [1], PointerToSymbolTable and NumberOfSymbols should be zero for an image in the COFF file header. Currently the COFF file header is hardcoded on ARM and these two members are not zero. This updates the hardcoded structure to clear these two members, as well as setting the flag IMAGE_FILE_LOCAL_SYMS_STRIPPED so that we can generate compliant *.efi images. [1] https://docs.microsoft.com/zh-cn/windows/desktop/Debug/pe-format Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2018-12-02x86: efi: app: Generate Microsoft PE format compliant imageBin Meng
Per Microsoft PE Format documentation [1], PointerToSymbolTable and NumberOfSymbols should be zero for an image in the COFF file header. Currently U-Boot is generating u-boot-app.efi in which these two members are not zero. This updates the build rules to tell linker to remove the symbol table completely so that we can generate compliant *.efi images. [1] https://docs.microsoft.com/zh-cn/windows/desktop/Debug/pe-format Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2018-12-02x86: efi: payload: Generate Microsoft PE format compliant imageBin Meng
Per Microsoft PE Format documentation [1], PointerToSymbolTable and NumberOfSymbols should be zero for an image in the COFF file header. Currently U-Boot is generating u-boot-payload.efi image in which these two members are not zero. This updates the build rules to tell linker to remove the symbol table completely so that we can generate compliant *.efi images. [1] https://docs.microsoft.com/zh-cn/windows/desktop/Debug/pe-format Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2018-12-01Merge tag 'for-master-20181130' of git://git.denx.de/u-boot-rockchipTom Rini
Improvements: - RK3188 USB-UART functionality - errors triggering a hard-stop in SPL on the RK3399 are reported - Rockchip RV1108 (SoC) support - MicroCrystal RV3029 (RTC) DM driver Fixes: - RK3188 early UART setup - limit SD-card frequency to 40MHz on the RK3399-Q7 - MIPI fixes - RK3399 CPUB clock initialisation
2018-11-30Merge tag 'pull-30nov18' of git://git.denx.de/u-boot-dmTom Rini
Fix sound on sandbox Convert TPM fully to DM Tidy up sandbox I2C emulation Add a 'make qcheck' target for faster testing A few other misc things (dropped the final patch which breaks clang for some reason)
2018-11-30Merge tag 'mips-pull-2018-11-30' of git://git.denx.de/u-boot-mipsTom Rini
- MIPS: MT76xx: minor fixes and updates to gardena-smart-gateway board
2018-11-30rockchip: rk3188: use board_debug_uart_init() for UART io initKever Yang
Sync with other rockchip SoCs, use board_debug_uart_init() to init default UART iomux. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30rockchip: rk3399: Initialize CPU B clock.Christoph Muellner
This patch sets the PLL of CPU cluster B (BPLL) to 600 MHz. This decreases the boot time of Linux 4.19 by about 8%. The 600 MHz are inspired by the 600 MHz used for LPLL initialization (came in with commit 9f636a249c1). Tested on RK3399-Q7 on Haikou base board. Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30ARM: dts: rockchip: Add rv1108 USB OTG pinctrlOtavio Salvador
This adds the definitions need to use the USB OTG in rv1108 board. This has been tested using USB Mass Storage to export and program a eMMC device. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30ARM: rockchip: rv1108: Add a board_usb_init for USB OTGOtavio Salvador
Like it is done for other Rockchip SoCs, introduce a board_usb_init() function so that USB OTG can be functional on rv1108 too. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30ARM: dts: rockchip: Add rv1108 eMMC pinctrlOtavio Salvador
This adds the pinctrl handles to enable the use of eMMC on custom boards (as minievk) and makes it easier for later addition. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30ARM: rockchip: rv1108: Sync clock with vendor treeOtavio Salvador
Make adjustments to the rv1108 clock driver in order to align it with the internal Rockchip version. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30rockchip: rk3399-puma: reduce sd card max-frequency to 40MHzPhilipp Tomsich
Some SanDisk Ultra cards trigger intermittent errors on detection resulting in an -EOPNOTSUPP, when running at 50MHz. Waveform analysis suggest that the level shifters that are used on the RK3399-Q7 module (for voltage translation between the on-module voltages and the 3.3V required on the card-edge) don't handle clock rates at or above 48MHz properly. This change reduces the maximum frequency on the external SD-interface to 40MHz (for a safety margin of 20%). Reported-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
2018-11-30rockchip: rk3399: spl: always report errors triggering a hard stopPhilipp Tomsich
The RK3399 SPL has two cases that may end in a hard-stop: if either the pinctrl can not be initialised or if the DRAM fails to initialise. Both have previously not triggered an error message unless DEBUG was defined (i.e. both used debug() to print the error). This converts both error messages to be printed using pr_err() to ensure that some output points to the cause of the hard-stop. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30rockchip: rk3188: fix early uart setupHeiko Stuebner
Commit 7a6d7d3e1279 ("rockchip: pinctrl: rk3188: Move the iomux definitions into pinctrl-driver") moved the iomux settings out of the grf header to prevent conflicts with the iomux definitions of other rockchip socs. This also breaks the early uart setup, as the iomux for uart2 are needed. To fix that just put the tiny amount of needed iomux definitions next to the early uart code. Fixes: 7a6d7d3e1279 ("rockchip: pinctrl: rk3188: Move the iomux definitions into pinctrl-driver") Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30rockchip: rk3188: add support for usb-uart functionalityHeiko Stuebner
Rockchip socs can route the debug uart pins through the d+ and d- pins of one specific usbphy per soc. Add a config option and implement the setting on the rk3188. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [Fixed up to mark grf as maybe unused:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30mips: mt7628: Change compatible property of the ethernet DT nodeStefan Roese
As the driver has been changed to be more specific, the DT compatible property also needs to be adapted. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-11-30Merge git://git.denx.de/u-boot-marvellTom Rini
- Some Kirkwood boards converted to DM_SPI by Chris - New Armada-385 SoC revision printed by Chris - Ethernet enable on mcbin by Baruch - Support 2 DRAM banks on Armada-8k boards by Baruch
2018-11-30ARM: mvebu: add revision id for Armada-385 B0Chris Packham
Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-11-30arm: mvebu: mcbin: dts: enable 1G network interfaceBaruch Siach
Describe the 1Gb network interface with on-board 88E1512 PHY. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-11-30arm64: zynqmp: Add mini mtest configurationMichal Simek
This configuration is useful when you want to run small u-boot and perform DDR memory test to make sure that DDR is properly configured. It is use for board bringup because alternative u-boot memory tests is quite good. Configuration is running out of OCM. As is done for others mini configurations 0x80 bytes for variables is enough and only default variables are stored there. Alternative memtest is enabled and also 2GB of DDR via DTS files. Configuration is enabling ZYNQMP_PSU_INIT_ENABLED and include psu_init() from zcu102 for testing purpose. In case of size issue this can be moved to SPL configuration as is done for mini_qspi configuration but it is not a problem now. Log: U-Boot 2018.11-00268-gbd58b8ba8915 (Nov 29 2018 - 15:33:35 +0100) Model: ZynqMP MINI Board: Xilinx ZynqMP DRAM: WARNING: Initializing TCM overwrites TCM content 2 GiB EL Level: EL3 In: dcc Out: dcc Err: dcc ZynqMP> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-29Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini
2018-11-29Merge tag 'u-boot-amlogic-20181126' of git://git.denx.de/u-boot-amlogicTom Rini
Cleanup and update towards support for Amlogic Meson AXG SoCs : - mmc: meson-gx: Add AXG compatible - net: designware: add meson meson compatibles - Amlogic Meson cleanup for AXG SoC support
2018-11-29sandbox: Use memmove() to move overlapping regionsSimon Glass
The use of strcpy() to remove characters at the start of a string is safe in U-Boot, since we know the implementation. But in os.c we are using the C library's strcpy() function, where this behaviour is not permitted. Update the code to use memmove() instead. Reported-by: Coverity (CID: 173279) Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Alexander Graf <agraf@suse.de>
2018-11-29sandbox: Enable soundSimon Glass
Now that the buffer-overflow bug is fixed, we can enable sound on sandbox. Drop the code which exits early. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-29sound: sandbox: Use the correct frequencySimon Glass
At present we request a particular frequency but we may not get the exact same frequency in response. So use the actual frequency for generation of the square wave. This ensures that the pitch remains accurate on all host machines. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-29sound: Add sample rate as a parameter for square waveSimon Glass
At present this value is hard-coded in the function that generates a square wave. Since sample rates vary between different hardware, it makes more sense to have this as a parameter. Update the function and its users. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-29dm: sandbox: i2c: Use new emulator parent uclassSimon Glass
Update the device tree, sandbox i2c driver and tests to use the new emulation parent to hold emulators. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-29arm: socfpga: fix SPL booting from fpga OnChip RAMSimon Goldschmidt
This patch prevents disabling the FPGA bridges when SPL or U-Boot is executed from FPGA onchip RAM. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-11-29arm: socfpga: make socfpga_socrates_defconfig boot from QSPISimon Goldschmidt
This fixes the board's dts to supply SPL with QSPI info. The EBV Socrates board has DIP switches to boot from SD card or QSPI, so let's fix its defconfig to work for both cases. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-11-29dts: arm: socfpga: merge gen5 devicetrees from linuxSimon Goldschmidt
Add -u-boot.dtsi files to keep the current U-Boot behaviour: - add u-boot,dm-pre-reloc where required - disable watchdog - set uart clock frequency - add gpio bank-name properties where appropriate: - make qspi work (add alias for spi0, fix compatible for flash) - enable usb (status okay, add alias for udc0) Adapt board dts files that are not in Linux to keep their old behaviour. Change licenses to SPDX. (Patman warnings/errors are in 1:1 copied files from Linux) Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-11-29spi: cadence_qspi: use "cdns,qspi-nor" as compatibleSimon Goldschmidt
Linux uses "cdns,qspi-nor" as compatible string for the cadence qspi driver, so change driver, docs and all device trees. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
generated by cgit (git 2.34.1) at 2024-12-28 12:35:10 +0000