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2018-01-14arm: imx: hab: Make authenticate_image return intBryan O'Donoghue
Both usages of authenticate_image treat the result code as a simple binary. The command line usage of authenticate_image directly returns the result code of authenticate_image as a success/failure code. Right now when calling hab_auth_img and test the result code in a shell a passing hab_auth_img will appear to the shell as a fail. The first step in fixing this behaviour is to fix-up the result code return by authenticate_image() itself, subsequent patches fix the interpretation of authenticate_image so that zero will return CMD_RET_SUCCESS and non-zero will return CMD_RET_FAILURE. The first step is fixing the return type in authenticate_image() so do that now. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Sven Ebenfeld <sven.ebenfeld@gmail.com> Cc: George McCollister <george.mccollister@gmail.com> Cc: Breno Matheus Lima <brenomatheus@gmail.com> Tested-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-01-12Merge git://git.denx.de/u-boot-tegraTom Rini
2018-01-12ARM: Tegra186: calculate load addresses at bootStephen Warren
In the presence of potentially fragemented memory, we cannot hard-code addresses into environment variables such as kernel_addr_r. Instead, we must calculate those addresses at run-time based on available memory locations. Implement the code to perform such runtime calculation, based on requirements described in environment variables, to allow the user full control over the allocation. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-01-12ARM: Tegra186: don't map memory not in RAM banksStephen Warren
Tegra186 currently restricts its DRAM usage to entries in the /memory node in the DTB passed to it. However, the MMU configuration always maps the entire first 2GB of RAM. This could allow the CPU to speculatively access RAM that isn't part of the in-use banks. This patch switches to runtime construction of the table that's used to construct the MMU translation tables, and thus prevents access to RAM that's not part of a valid bank. Note: This patch is intended to prevent access to RAM regions which U-Boot does not need to access, with the primary purpose of avoiding theoretical speculative access to physical regions for which the HW will throw errors (e.g. carve-outs that the CPU has no permission to access at a bus level, bad ECC pages, etc.). In particular, this patch is not deliberately related to the speculation-related security issues that were recently announced. The apparent similarity is a coincidence. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-01-12ARM: Tegra186: search for best RAM bankStephen Warren
In the future, the list of DRAM regions passed to U-Boot in the DTB may be quite long and fragmented. Due to this, U-Boot must search through the regions to find the best region to relocate into, rather than relying on the current assumption that the top of bank 0 is a reasonable relocation target. This change implements such searching. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-01-12ARM: bootm: don't assume sp is in DRAM bank 0Stephen Warren
arch_lmb_reserve() currently assumes that the stack pointer is within DRAM bank 0. This is not necessarily true. Enhance the code to search through DRAM banks until the bank that does contain SP is found, and then reserve the tail of that bank. Fixes: 2d1916e48bd8 ("ARM: add flat device tree support") Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-01-12ARM: Tegra186: mem parsing fixes from downstreamStephen Warren
Apply a few small fixes for the DTB /memory node parsing from NVIDIA's downstream U-Boot: - Allow arbitrary number of DRAM banks. - Correctly calculate the number of DRAM banks. - Clip PCIe memory in the same way as U-Boot CPU memory use. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-01-12ARM: tegra: use LINUX_KERNEL_IMAGE_HEADERStephen Warren
Enable CONFIG_LINUX_KERNEL_IMAGE_HEADER for all 64-bit Tegra boards. cboot (the boot SW that runs before U-Boot) will eventually use this information. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-01-12ARMv8: add optional Linux kernel image headerStephen Warren
Allow placing a Linux kernel image header at the start of the U-Boot binary. This is useful since the image header reports the amount of memory (BSS and similar) that U-Boot needs to use, but that isn't part of the binary size. This can be used by the code that loads U-Boot into memory to determine where to load U-Boot, based on other users of memory. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-01-12ARM: tegra: use CONFIG_SYS_INIT_SP_BSS_OFFSETStephen Warren
Enable CONFIG_SYS_INIT_SP_BSS_OFFSET for all 64-bit Tegra boards. Place the stack/... 512KiB from the end of the U-Boot binary. This should be plenty to accommodate the current DTBs (max 64 KiB), early malloc region (6KiB), stack usage, and plenty of slack, while still not placing it too far away from the U-Boot binary. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-01-12ARMv8: Allow dynamic early stack pointerStephen Warren
U-Boot typically uses a hard-coded value for the stack pointer before relocation. Implement option SYS_INIT_SP_BSS_OFFSET to instead calculate the initial SP at run-time. This is useful to avoid hard-coding addresses into U-Boot, so that can be loaded and executed at arbitrary addresses and thus avoid using arbitrary addresses at runtime. This option's value is the offset added to &_bss_start in order to calculate the stack pointer. This offset should be large enough so that the early malloc region, global data (gd), and early stack usage do not overlap any appended DTB. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-01-12ARM: tegra: don't use CONFIG_SPL_TEXT_BASE when no SPLStephen Warren
64-bit Tegra don't use SPL, and soon won't define CONFIG_SPL_TEXT_BASE when building. Fix the binman .dts file so that it doesn't use undefined values. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-01-12ARM: imx: cm_fx6: export board and soc info to envChristopher Spinrath
Like many other i.MX6 based boards, there are multiple variants of the cm-fx6 module featuring different SoC variants. Furthermore, the module can be paired with multiple baseboards. At the same time modern distribution like Fedora require U-Boot to select a proper devicetree which depends on the SoC variant and the baseboard. Thus, export the SoC variant and the actual board to the environment following the conventions of other i.MX6 devices (e.g. the NXP boards) such that the environment can select a devicetree file to load. For now, we only know for sure that the cm-fx6 module and the SB-fx6m baseboard amount to a Utilite Computer variant (depending on the SoC). Further combinations may be added in the future; e.g. CompuLab's evaluation board once someone can verify the identification string stored in its eeprom. Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
2018-01-12arm: imx: Rework i.MX specific commands to be excluded from SPLTom Rini
The "clocks" and "bootaux" commands are only usable in full U-Boot, not SPL, so do not link them inside of SPL. Rework a little of the bootaux related code to make use of __weak and declare parts of it static as it's local to the file. Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-01-12imx7: spl: Add support for MMC3, SD3 and NAND boot devicesEran Matityahu
Signed-off-by: Eran Matityahu <eran.m@variscite.com>
2018-01-12imx7: spl: Use SPL boot device MMC1 for all of the SOCs MMC/SD boot devicesEran Matityahu
Use only one SPL MMC device, similarly to the iMX6 code Signed-off-by: Eran Matityahu <eran.m@variscite.com>
2018-01-12imx: mx6ull-14x14-evk: enable DM QSPI driverPeng Fan
To support QSPI DM driver - Add spi0 alias for qspi node. Which is used for bus number 0. - Modify the n25q256a@0 compatible property to "spi-flash". - Modify spi4 (gpio_spi) node to spi5 - Define DM SPI/QSPI related config to enable QSPI Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-01-12mx6: ddr: Do not access MMDC_P1_BASE_ADDR on i.MX6ULLFabio Estevam
i.MX6ULL also does not have a MMDC_P1_BASE_ADDR, so do not try to access it. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Stefano Babic <ssbabic@denx.de>
2018-01-12ARM: imx: Introduce dts for i.MX6SX-SDBPeng Fan
Introduce dts from Kernel commit commit 71ee203389f7cb1c("Merge tag 'scsi-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi") Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com>
2018-01-12mx6: Support SKS-Kinkel sksimx6 BoardStefano Babic
Board has 1GB RAM and boots from SD Card U-Boot SPL 2018.01-rc3-00005-ga1898b8 (Jan 02 2018 - 13:48:54) BT_FUSE_SEL already fused, will do nothing Trying to boot from MMC1 U-Boot 2018.01-rc3-00005-ga1898b8 (Jan 02 2018 - 13:48:54 +0100) CPU: Freescale i.MX6DL rev1.2 996 MHz (running at 792 MHz) CPU: Commercial temperature grade (0C to 95C) at 40C Reset cause: POR I2C: ready DRAM: 1 GiB MMC: FSL_SDHC: 0 In: serial Out: serial Err: serial Net: FEC [PRIME] Signed-off-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-01-12riscv: Modify generic codes to support RISC-VRick Chen
Support common commands bdinfo and image format, also modify common generic flow for RISC-V. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-01-12riscv: Add Kconfig to support RISC-VRick Chen
Add Kconfig and makefile for RISC-V Also modify MAINTAINERS for it. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2018-01-12riscv: nx25: include: Add header files to support RISC-VRick Chen
Add header files for RISC-V. Cache, ptregs, data type and other definitions are included. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com>
2018-01-12riscv: nx25: dts: Add AE250 dts to support RISC-VRick Chen
AE250 is the Soc using NX25 cpu core base on RISC-V arch. Details please see the doc/README.ae250. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com>
2018-01-12riscv: nx25: lib: Add relative lib funcs to support RISC-VRick Chen
Add makefile, interrupts.c and boot.c,... functions to support RISC-V arch. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2018-01-12riscv: cpu: Add nx25 to support RISC-VRick Chen
Add Andes nx25 cpu core (called AndesStar V5) to support RISC-V arch Verifications: 1. startup and relocation ok. 2. boot from rom or ram both ok. 2. timer driver ok. 3. uart driver ok 4. mmc driver ok 5. spi driver ok. 6. 32/64 bit both ok. Detail verification message please see doc/README.ae250. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2018-01-11Merge git://git.denx.de/u-boot-sunxiTom Rini
2018-01-11Merge git://git.denx.de/u-boot-videoTom Rini
2018-01-11Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
2018-01-11Merge git://git.denx.de/u-boot-socfpgaTom Rini
2018-01-11Merge git://git.denx.de/u-boot-usbTom Rini
2018-01-11mach-omap2: add AM335x Display PLL register definitionHannes Schmelzer
Adds the register definition of the Display DPLL Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Reviewed-by: Anatolij Gustschin <agust@denx.de>
2018-01-10ls1088ardb: Add SD Secure boot target supportSumit Garg
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> [YS: run moveconfig.py -s] Reviewed-by: York Sun <york.sun@nxp.com>
2018-01-10armv8: fsl-layerscape: SPL size reductionSumit Garg
Compile-off mp.c and libfdt.c in case of SPL build. SPL size reduces by approx 2k. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-01-10armv8: Implement workaround for Cortex-A53 erratum 855873Alison Wang
855873: An eviction might overtake a cache clean operation Workaround: The erratum can be avoided by upgrading cache clean by address operations to cache clean and invalidate operations. For Cortex-A53 r0p3 and later release, this can be achieved by setting CPUACTLR.ENDCCASCI to 1. This patch is to implement the workaround for this erratum. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-01-10drivers/misc: Share qbman init between archsAhmed Mansour
This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-01-10armv8: layerscape: sata: refine port register configurationYuantian Tang
Sata registers PP2C and PP3C are used to control the configuration of the PHY control OOB timing for the COMINIT/COMWAKE parameters respectively. Calculate those parameters from port clock frequency. Overwrite those registers with calculated values to get better OOB timing. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-01-10armv8: ls1088 : MC alignment should always be fixed to 512MBAshish Kumar
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-01-10Merge git://git.denx.de/u-boot-marvellTom Rini
2018-01-10build: Drop CONFIG_SPL_BUILD guards in some casesTom Rini
Given gcc-6.1 and later we can now safely have strings discarded when the functions are unused. This lets us drop certain cases of not building something so that we don't have the strings brought in when the code was discarded. Simplify the code now by dropping guards we don't need now. Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Chander Kashyap <k.chander@samsung.com> Cc: Thomas Abraham <thomas.ab@samsung.com> Cc: Vipin Kumar <vipin.kumar@st.com> Cc: Wenyou Yang <wenyou.yang@microchip.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2018-01-10BCM283x ALT5 function for JTAG pinsHenry Zhang
BCM2835 ARM Peripherals doc shows gpio pins 4, 5, 6, 12 and 13 carry altenate function, ALT5 for ARM JTAG Signed-off-by: Henry Zhang <henryzhang62@yahoo.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-01-10ARM: DTS: stm32: add MMC nodes for stm32f746-disco and stm32f769-discoPatrice Chotard
Add DT nodes to enable ARM_PL180_MMCI IP support for STM32F746 and STM32F769 discovery boards There is a hardware issue on these boards, it misses a pullup on the GPIO line used as card detect to allow correct SD card detection. As workaround, cd-gpios property is not present in DT. So SD card is always considered present in the slot. Signed-off-by: Christophe Priouzeau <christophe.priouzeau@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-01-10ARM: DTS: stm32: add SDIO controller support for stm32f469-discoPatrice Chotard
STM32F469 SoC uses an arm_pl180_mmci SDIO controller. Signed-off-by: Andrea Merello <andrea.merello@gmail.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-01-10board: stm32: add stm32f469-discovery board supportPatrice Chotard
This board offers : _ STM32F469NIH6 microcontroller featuring 2 Mbytes of Flash memory and 324 Kbytes of RAM in BGA216 package _ On-board ST-LINK/V2-1 SWD debugger, supporting USB reenumeration capability: _ Mbed-enabled (mbed.org) _ USB functions: USB virtual COM port, mass storage, debug port _ 4 inches 800x480 pixel TFT color LCD with MIPI DSI interface and capacitive touch screen _ SAI Audio DAC, with a stereo headphone output jack _ 3 MEMS microphones _ MicroSD card connector _ I2C extension connector _ 4Mx32bit SDRAM _ 128-Mbit Quad-SPI NOR Flash _ Reset and wake-up buttons _ 4 color user LEDs _ USB OTG FS with Micro-AB connector _ Three power supply options: _ Expansion connectors and Arduino™ UNO V3 connectors Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-01-10ARM: DTS: stm32: add stm32f469-disco-u-boot dts filePatrice Chotard
_ Add gpio compatible and aliases for stm32f469 _ Add FMC sdram node _ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl, pwrcfg and gpio nodes. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-01-10ARM: DTS: add STM32F469 Discovery board supportPatrice Chotard
This DT file comes from kernel v4.15-rc1 stm32f469-pinctrl.dtsi header has been updated with correct STMicroelectronics Copyright. Remove the paragraph about writing to the Free Software Foundation's mailing address as requested by checkpatch. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-01-10board: stm32f429-disco: switch to DM STM32 pinctrl and gpio driverPatrice Chotard
Use available DM stm32f7_gpio.c and pinctrl_stm32.c drivers instead of board GPIO initialization. Remove stm32_gpio.c which is no more used and migrate structs stm32_gpio_regs and stm32_gpio_priv into arch-stm32f4/gpio.h to not break compilation. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-01-10board: stm32f429-disco: switch to DM STM32 clock driverPatrice Chotard
Use available DM clk_stm32f.c driver instead of dedicated mach-stm32/stm32f4/clock.c. Migrate periph_clock defines from stm32_periph.h directly in CLK driver. These periph_clock defines will be removed when STMMAC, TIMER2 and SYSCFG drivers will support DM CLK. Enable also CLK flag. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-01-10mach-stm32: stmf32f4: timer: remove clock_get() callPatrice Chotard
In order to use common clock driver between STM32F4 and STM32F7, remove clock_get() call As APB_PSC is always set to 2, only case when clock_get(CLOCK_AHB) != clock_get(CLOCK_APB1) is kept Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-01-10board: stm32f429-disco: switch to DM STM32 serial driverPatrice Chotard
Remove serial_stm32.c driver and uart init from board file, use available DM serial_stm32x7.c driver compatible for STM32F4/F7 and H7 SoCs. The serial_stm32x7.c driver will be renamed later with a more generic name as it's shared with all STM32 Socs. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
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