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2014-02-19zynq: Add support for U-BOOT SPLMichal Simek
SPL is using ps7_init.c/h files which are generated from design tools which have to be copied to boards/xilinx/zynq folder before compilation. BSS section is moved to SDRAM because fat support requires more space than SRAM size. Added: - MMC and QSPI support - Boot OS directly from SPL - Enable SPL command Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
2014-02-19zynq: Update CLK in bdinfoMichal Simek
ARM has specific clk entries which should be also setup. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-19zynq: Implement dump clock commandSoren Brinkmann
Enable and implement dump clock command which shows soc frequencies. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-19net: zynq_gem: Calculate clock dividers dynamicallySoren Brinkmann
Remove hard coded clock divider setting and use the Zynq clock framework to dynamically calculate appropriate dividers at run time. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-19net: zynq_gem: Move RCLK details out of driverSoren Brinkmann
The GEM driver should not need to know about Zynq specific details of RCLK related registers and bitfields in the SLCR. Move those details to the slcr driver. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-19zynq: timer: Fix hangs if network activity attempted after about one hourMichal Simek
Cortex-A9 MPCore TRM' from ARM (ARM DDI 0407G ID072711) describes in the section 4.1.1 how this value calculation should be done. This patch fixes the problem if network activity such as ping or tftp is attempted after u-boot has been idle for an hour, it hangs, and cannot control-C out of it. Signed-off-by: Uday Hegde <udayh@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-19zynq: timer: Migrate to zynq clock frameworkSoren Brinkmann
Remove hardcoded frequencies in favor of Zynq clock framework. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-19zynq: Provide a framework to read clock frequenciesSoren Brinkmann
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-19zynq: serial: Simplify serial driver initializationMichal Simek
Define both serial uarts in the driver and return default uart based on board configuration. - Move baseaddresses to hardware.h - Define default baudrate and clock values Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-19zynq: Move bootmode to headersMichal Simek
These numbers will be reused by SPL. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-19zynq: Enable dcache supportMichal Simek
Enable dcache. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-19Merge branch 'u-boot-pxa/master' into 'u-boot-arm/master'Albert ARIBAUD
2014-02-17Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini
2014-02-17Merge branch 'master' of git://git.denx.de/u-boot-mmcTom Rini
2014-02-14ARM: bcm2835: fix mbox POWER_STATE_RESP_ON valueStephen Warren
Typo: The correct value is 1 not 2. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
2014-02-13zynq: Fix elf header generationMichal Simek
This patch is here because of: "arm: keep all sections in ELF file" (sha1: 47ed5dd031d7d2c587e6afd386e79ccec1a1b7f7) Our tools expect to have elf with only LOAD header. Without this fix also PHDR, INTERP and DYNAMIC headers are available in ELF. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-13ARM: bcm2835: config.mk isn't neededStephen Warren
The entries in config.mk were needed so that U-Boot could be built with an old version of the Raspberry Pi Foundation's toolchain. Without them, the build would error out with: ...-ld: error: .../libgcc.a(_bswapsi2.o) uses VFP register arguments, u-boot does not However, none of the 3 toolchains in the latest version of their tools.git, nor the Ubuntu/Linaro ARM compilers in at least Ubuntu Quantal or Saucy, need these options set in order to compile a working U-Boot. Hence, remove the options for simplicity. Reported-by: Tom Rini <trini@ti.com> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Andreas Färber <afaerber@suse.de>
2014-02-13Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD
2014-02-10exynos: clock: use the clear and set bits macros.Inha Song
Use setbits/clrbits macro instead of readl/writel function. (Suggested by Wolfgang) Signed-off-by: Inha Song <ideal.song@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-02-10exynos: clock: fixed that cfg is set to wrong value.Inha Song
This patch fixed that cfg value is set to wrong value. Because it didn't read the related register. Signed-off-by: Inha Song <ideal.song@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-02-07SPL: Add CONFIG_SUPPORT_EMMC_BOOT support to CONFIG_SPL_FRAMEWORKTom Rini
We use the switch CONFIG_SUPPORT_EMMC_BOOT today to enable some additional features of the eMMC boot partitions. Add support for being told that we have booted from one of these partitions to the spl framework and implement this on TI OMAP/related. Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Signed-off-by: Tom Rini <trini@ti.com> Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-02-07MMC: DWMMC: Correct the CLKDIV register valueRajeshwari S Shinde
This patch corrects the divider value written to CLKDIV register. Since SDCLKIN is divided inside controller by the DIVRATIO value set in the CLKSEL register, we need to use the same output clock value to calculate the CLKDIV value. as per user manual: cclk_in = SDCLKIN / (DIVRATIO + 1) Input parameter to mmc_clk is changed to dwmci_host, since we need the same to read DWMCI_CLKSEL register. This improves the read timing values for channel 0 on SMDK5250 from 0.288sec to 0.144sec Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-02-07arc: add library functionsAlexey Brodkin
These are library functions used by ARC700 architecture. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Francois Bedard <fbedard@synopsys.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Heiko Schocher <hs@denx.de>
2014-02-07arc: add cpu filesAlexey Brodkin
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Francois Bedard <fbedard@synopsys.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Heiko Schocher <hs@denx.de>
2014-02-07arc: add architecture header filesAlexey Brodkin
These are header files used by ARC700 architecture. Also note that "arch-arc700/hardware.h" is only required for compilation of "designware_i2c" driver which refers to "asm/arch/hardware.h". It would be good to fix mentioned driver sometime soon but it will cause changes in ARM board configs that use "designware_i2c". Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Francois Bedard <fbedard@synopsys.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Heiko Schocher <hs@denx.de>
2014-02-07blackfin: Initialize the EMAC VLAN with proper default valueAaron Wu
EMAC_VLANx regs is not properly initiallized in u-boot, once it's overwrite in the kernel when DSA enabled, hot reset will lead to bringing up EMAC fail in u-boot. Signed-off-by: Aaron Wu <Aaron.Wu@analog.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2014-02-07blackfin: Change SMC dcplb entry flag to cover 16M address regionSonic Zhang
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2014-02-07blackfin: init bss earlyBob Liu
Signed-off-by: Bob Liu <lliubbo@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2014-02-07blackfin: The logic of the BF609 macro is opposite.Sonic Zhang
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2014-02-07arm:s5pc110: add cpu revisionPiotr Wilczek
This patch adds s5p_cpu_rev. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-02-07arm:exynos: add cpu revisionPiotr Wilczek
This patch enables to read cpu revision on Exynos CPU. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-02-06ARM: IXP: Remove the IXP architecture supportMarek Vasut
The architecture is unmaintained and dead, remove it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Michael Schwingen <michael@schwingen.org> Cc: Tom Rini <trini@ti.com>
2014-02-05exynos: pinmux: remove unnecessary routineMinkyu Kang
Because of the list of peripherals is not sequential, such a routine does not check for valid correctly. Error check will be done when call the exynos_pinmux_config function. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
2014-02-05exynos: pinmux: remove unnecessary defineMinkyu Kang
The value of PERIPH_ID_COUNT was wrong, and unnecessary. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-02-05exynos: pinmux: sort the list of peripheralsMinkyu Kang
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Acked-by: Rajehswari Shinde <rajeshwari.s@samsung.com>
2014-02-04Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini
2014-02-04microblaze: Add SPL supportMichal Simek
Add support for U-BOOT SPL. NOR and RAM mode are supported. There are 3 images in NOR flash. u-boot.img, dtb and kernel. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-04microblaze: Report priviledged or stack protection exceptionMichal Simek
Just list one more exception. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-04microblaze: Show u-boot bannerMichal Simek
It is nice to see u-boot version. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-03ARM: tegra: add DT files for Tegra124 and Venice2Tom Warren
These are fairly complete, and near-clones of Tegra114 Venice, with an additional I2C port, and MMC address changes for Tegra124. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-02-03ARM: tegra: add common (shared) CPU filesTom Warren
These files are used by both SPL and main U-Boot. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-02-03ARM: tegra: Add CPU (armv7) files for Tegra124Tom Warren
These files are for code that runs on the CPU (A15) on Tegra124 boards. At this time, there is no A15-specific code here. The warmboot/LP0 files aren't included as that code hasn't been ported yet. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-02-03ARM: tegra: add SPL/AVP (arm720t) CPU files for Tegra124Tom Warren
This provides SPL support for Tegra124 boards - AVP early init, plus CPU (A15) init/jump to main U-Boot. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-02-03ARM: tegra: add/edit headers for Tegra124Tom Warren
These headers define the Tegra124 hardware. Add them to the usual place. Add Tegra124 chip ID/SKU ID definitions to common headers. There's no real HW change on Tegra124 for 90% of the toys, so it might make sense for a future patch to unify some of the content of these files in a common location. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-02-03ARM: tegra: fix a typo in the tegra114.dtsiStephen Warren
The reg property for node spi@7000d800 was wrong. Fix it to match the HW. This change was verified against the Linux kernel. Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-02-03ARM: tegra: remove a conditional for CSITE rateStephen Warren
There's already an SoC-specific conditional in cpu.h to determine the PLLP rate. Define the CSITE clock rate inside the same conditional, so that we can remove a conditional from clock_enable_coresight(). This means one less place to update the code for new SoCs. Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-02-03ARM: tegra: enable PLLX only once it's been fully configuredStephen Warren
This programming sequence is correct per Jimmy Zhang, and makes sense too! Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-02-03ARM: tegra: pass just partition ID to power_partition()Stephen Warren
Pass just the partition ID to power_partition(), rather than also passing the partition's status register mask too. This makes it simpler to get call-sites correct, since they don't need to pass two different values that define the same thing and must match. Consequently, we can remove the mask definitions from pmc.h. Suggested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-02-03ARM: tegra: misc cleanups triggered by Tegra124 reviewStephen Warren
Use a named constant for the PLL lock bit in enable_cpu_clocks(). Construct the complete value of pmc_pwrgate_toggle, rather than doing a read-modify-write; the register is simple enough and doesn't need to maintain state between operations. Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-02-03ARM: tegra: don't exceed AVP limits when configuring PLLPJimmy Zhang
Based on the Tegra TRM, the system clock (which is the AVP clock) can run up to 275MHz. On power on, the default sytem clock source is set to PLLP_OUT0. In function clock_early_init(), PLLP_OUT0 will be set to 408MHz which is beyond system clock's upper limit. The fix is to set the system clock to CLK_M before initializing PLLP, and then switch back to PLLP_OUT4, which has an appropriate divider configured, after PLLP has been configured Implement this logic in new function tegra30_set_up_pllp(), which sets up PLLP and all PLLP_OUT* dividers, and handles the AVP clock switching. Remove the duplicate PLLP setup from pllx_set_rate() and adjust_pllp_out_freqs(). Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> [swarren, significantly refactored the change] Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
generated by cgit (git 2.34.1) at 2025-01-01 18:29:58 +0000