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2019-07-04ARM: meson: add unique MAC address generationNeil Armstrong
Add support for generating an unique MAC address using the SoC internal serial number from the Secure Monitor interface. The algorithm generates an unicast locally administered 6bytes minus 2bits address using an crc16 of the serial for the top 16bits with the lower 2 bits masked to setup the unicast locally administered property and a crc24 for the lower 24bits. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-07-04ARM: meson: sm: Add secure monitor calls to retrieve SoC serial numberNeil Armstrong
The Secure Monitor interface permits retrieving the SoC Serial Number, add a function to retrieve it. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-07-02rockchip: rk3288: enable TPL for tinker-boardKever Yang
All the config for TPL has been update, we can enable the TPL. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-02rockchip: dts: rk3288-tinker: enable sdmmc pinctrl node in splKever Yang
rockchip pinctrl driver has update to use dts, so we need to add the pinctrl config in SPL for sdmmc. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-02rockchip: dts: tinker: migrate the dm-pre-reloc tag into -u-boot dtsKever Yang
Migrate all the "u-boot,dm-pre-reloc" tag from rk3288-tinker.dts into rk3288-tinker-u-boot.dtsi. When both board level and soc level '-u-boot.dtsi' files exist, we need to include the soc level 'rk3288-u-boot.dtsi' manually. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-02rockchip: dts: rk3288: move reloc tag into -u-boot dtsKever Yang
Move all the tag "u-boot,dm-pre-reloc" from rk3288.dtsi into rk3288-u-boot.dtsi. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-02rockchip: rk3288: add separate TPL STACK addressKever Yang
TPL is at SRAM while other stage is at SDRAM, so it needs separate STACK. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-02rockchip: rk3288: enable TPL configs to chip levelKever Yang
More boards other than vyasa needs TPL, so enable the TPL configs at chip level instead of board level. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-02rockchip: dts: rk3399: rockpro64: Provide init voltageMark Kettenis
Add missing regulator-init-microvolt property to vdd_log regulator. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> (Rebase on latest u-boot-rockchip master) Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Change-Id: I13b24fb81e8ad269d7dbb0c7b67f5f4795d2e775
2019-06-29ARM: uniphier: move sg_set_{pinsel, iectrl} to more relevant placesMasahiro Yamada
Move the sg_set_pinsel macro to arch/arm/mach-uniphier/arm32/debug_ll.S since it is not used anywhere else. Move the C functions sg_set_{pinsel,iectrl} to debug-uart.c since they are not used anywhere else. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-06-29ARM: uniphier: remove unused init code for CONFIG_DEBUG_UARTMasahiro Yamada
debug_uart_init() is called from spl_board_init(), which is only compiled for SPL. For U-boot proper, _debug_uart_init() is unreachable, so dropped by the dead code elimination. Now that 64-bit SoCs of this SoC family no longer support SPL, debug-uart-ld20.c is never compiled. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-06-29ARM: uniphier: include <linux/io.h> from dram_init.cMasahiro Yamada
This file calls readl(), so needs to include <linux/io.h>. Currently, it relies on someone else including it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-06-29ARM: uniphier: remove unused sg_set_iectrl_range()Masahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-06-29ARM: uniphier: remove unused SC_DPLLOSCCTRLMasahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-06-29ARM: uniphier: fix build error for CONFIG_DEBUG_LL=yMasahiro Yamada
Commit e27d6c7d328c ("ARM: uniphier: simplify SoC ID get function") accidentally removed the macros needed to compile debug_ll.S Revive them. Fixes: e27d6c7d328c ("ARM: uniphier: simplify SoC ID get function") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-06-28Merge tag 'u-boot-imx-20190628' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx Fixes for 2019.07 - menlo board - allow SDB on Sabre - HAB for mx6sl - apalis board
2019-06-28Merge tag 'u-boot-stm32-20190628' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-stm STM32 MCU fixes/cleanup: - Fix SPL console for STM32F769 Discovery - Fix Memory Protection Unit size for STM32F4 series - Cleanup DT for STM32F746 Discovery
2019-06-28mach-stm32: Fix MPU region size dedicated to SDRAM for STM32F4Patrice Chotard
The MPU region dedicated for SDRAM for STM32F4 SoCs family was set to 16MB, but STM32F429 Evaluation board have 32MB of SDRAM. When kernel starts, only first 16MB of SDRAM are configured with XN (eXecute Never) bit disabled, whereas kernel is using 32MB. To avoid such situation in the future, extend this MPU region to 512MB as for STM32F7/H7. It fixes the following user land exception on STM32F429 Evaluation board : [ 1.713002] VFS: Mounted root (ext4 filesystem) readonly on device 179:2. [ 1.722605] devtmpfs: mounted [ 1.733057] Freeing unused kernel memory: 72K [ 1.737622] This architecture does not have kernel memory protection. [ 1.744070] Run /sbin/init as init process [ 1.906850] [ 1.906850] Unhandled exception: IPSR = 00000004 LR = fffffffd [ 1.914282] CPU: 0 PID: 1 Comm: init Not tainted 5.1.0-00002-gcf9ca5719954 #6 [ 1.921433] Hardware name: STM32 (Device Tree Support) [ 1.926601] PC is at 0x1a00b64 [ 1.929642] LR is at (null) [ 1.932669] pc : [<01a00b64>] lr : [<00000000>] psr: 01000000 [ 1.938993] sp : 01a5cfb0 ip : 00000000 fp : 00000000 [ 1.944269] r10: 01a43b00 r9 : 00000000 r8 : 00000000 [ 1.949564] r7 : 00000000 r6 : 00000000 r5 : 00000000 r4 : 00000000 [ 1.956168] r3 : 00000000 r2 : 00000000 r1 : 00000000 r0 : 00000000 [ 1.962701] xPSR: 01000000 [ 1.965506] CPU: 0 PID: 1 Comm: init Not tainted 5.1.0-00002-gcf9ca5719954 #6 [ 1.972658] Hardware name: STM32 (Device Tree Support) [ 1.978132] [<0000c009>] (unwind_backtrace) from [<0000b24f>] (show_stack+0xb/0xc) [ 1.986024] [<0000b24f>] (show_stack) from [<0000b947>] (__invalid_entry+0x4b/0x4c) Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-06-28ARM: dts: stm32: Remove useless u-boot, dm-pre-reloc in ↵Patrice Chotard
stm32f746-disco-u-boot.dtsi As in stm32f7-u-boot.dtsi these nodes already have "u-bootdm-pre-reloc" property, no need to add them again in stm32f746-disco-u-boot.dtsi. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-06-28ARM: dts: stm32: Add u-boot, dm-pre-reloc for usart1_pins_a for stm32f769-discoPatrice Chotard
This allow to get console output in SPL for stm32f769-disco. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-06-27ARM: dts: imx: m53menlo: Import M53Menlo DT from LinuxMarek Vasut
Import iMX53 M53Menlo device tree from Linux next-20190607 3f310e51ceb1 . Enable DT control in full U-Boot . Add U-Boot extras into separate DTSi, the GPIO controllers need to be inited early, otherwise m53_set_clock() won't be able to detect the correct CPU clock frequency by reading the GPIO. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2019-06-27ARM: dts: imx: imx53: Synchronize iMX53 DT with LinuxMarek Vasut
Synchronize iMX53 device tree from Linux next-20190607 3f310e51ceb1 , this is needed to get NFC, UART, USBOTG DT nodes. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2019-06-27mx6sl: hab: Fix pu_irom_mmu_enabled addressBreno Matheus Lima
According to hab.c code we have to notify the ROM code if the MMU is enabled or not. This is achieved by setting the "pu_irom_mmu_enabled" to 0x1. The current address in hab.c code is wrong for i.MX6SL, according to ROM map file the correct address is 0x00901c60. As we are writing in the wrong address the ROM code is not flushing the caches when needed, and the following HAB event is observed in certain scenarios: --------- HAB Event 1 ----------------- event data: 0xdb 0x00 0x14 0x41 0x33 0x18 0xc0 0x00 0xca 0x00 0x0c 0x00 0x01 0xc5 0x00 0x00 0x00 0x00 0x07 0xe4 STS = HAB_FAILURE (0x33) RSN = HAB_INV_SIGNATURE (0x18) CTX = HAB_CTX_COMMAND (0xC0) ENG = HAB_ENG_ANY (0x00) Update MX6SL_PU_IROM_MMU_EN_VAR to address this issue. Reported-by: Frank Zhang <frank.zhang@nxp.com> Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-06-26rockchip: rk3399: Enable TPL_BOARD_INITJagan Teki
Enable TPL_BOARD_INIT, this would help us to show TPL boot prints. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-06-26rockchip: rk3399: tpl: Mark printascii into debugJagan Teki
Now, we have spl_board_init which has TPL banner prints. So mark the 'U-Boot TPL board init' print into debug. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-06-26rockchip: rk3399: tpl: Add spl_board_initJagan Teki
Add spl_board_init for TPL, that have TPL banner will help to print tpl boot prints. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-06-26rockchip: rk3399: Enable SPL_BOARD_INITJagan Teki
Enable SPL_BOARD_INIT globally to rk3399, this would help to print the SPL banner during bootup. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-06-26rockchip: rk3399: Move u-boot, dm-pre-reloc of uart0, uart2Jagan Teki
u-boot,dm-pre-reloc for uart0, uart2 indeed u-boot specific properties. Move them into rk3399-u-boot.dtsi so the boards which enabled these node will available during SPL. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-06-26rockchip: rk3399: spl: Mark printascii into debugJagan Teki
Now, we have spl_board_init with preloader_console_init that indeed show SPL banner. So mark the 'U-Boot SPL board init' print into debug. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-06-26rockchip: rk3399: Support common spl_board_initJagan Teki
Support common spl_board_init by moving code from puma board file into, common rk3399-board-spl.c. Part of the code has sysreset-gpio, regulators_enable_boot_on but right now only puma board is using this with relevant config options rest remains common for all targets. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-06-26rockchip: rk3399: Get bl31.elf via BL31Jagan Teki
Right now rockchip platform need to copy bl31.elf into u-boot source directory to make use of building u-boot.itb. So, add environment variable BL31 like Allwinner SoC so-that the bl31.elf would available via BL31. If the builds are not exporting BL31 env, the make_fit_atf.py explicitly create dummy bl31.elf in u-boot root directory to satisfy travis builds and it will show the warning on console as WARNING: BL31 file bl31.elf NOT found, resulting binary is non-functional WARNING: Please read Building section in doc/README.rockchip Note, that the dummy bl31 files were created during not exporting BL31 case would be removed via clean target in Makefile. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-06-26rockchip: dts: rk3328: add rk3328-rock64.dtsMatwey V. Kornilov
rk3328-rock64.dts has been taken from Linux kernel commit cff6d1d6f88b ("arm64: dts: rockchip: enable HS200 for eMMC on rock64") with minor modifications (drop nodes not known by rk3328.dtsi). Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-06-26rockchip: Kconfig: enable SPL support for rk3328Kever Yang
Enable SPL support and some related option in Kconfig. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> [cherry picked from https://github.com/rockchip-linux/u-boot/commit/430b01462bf3f24aaf7920ae2587a6943c39ab5d with minor modifications] Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
2019-06-26rockchip: rk3328: add SPL board file supportKever Yang
rk3328 SPL is locate at dram, so do not have strict size limit, suppose to enable storage media controller driver, load ATF and U-Boot, then boot into ATF. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> [cherry picked from https://github.com/rockchip-linux/u-boot/commit/4ebe3968b683190cb8e5741aa7227b4fa7497874 with minor modifications] Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-06-22watchdog: tangier: Convert to use WDT classAndy Shevchenko
Convert legacy driver to use watchdog class. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Stefan Roese <sr@denx.de>
2019-06-22x86: Revert "Don't set up MTRRs in SPL"Andy Shevchenko
This breaks Intel Edison to work. It gets laggish and unable to boot kernel. Reverts commit 665cb18ea64aabbeb03d27a4c92ddec1baccb87a for now till better solution will be proposed. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2019-06-20armv8: fix typo in LINUX_KERNEL_IMAGE_HEADER checkMian Yousaf Kaukab
Fixes: 8163faf952 ARMv8: add optional Linux kernel image header Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Andreas Färber <afaerber@suse.de>
2019-06-20Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xxTom Rini
- PCIe driver change to support DM model - T2080QDS migrated to use PCIe DM model
2019-06-20Merge tag 'u-boot-stm32-20190619' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - Update STM32MP entry in MAINTAINERS - Handle correctly binding for g-tx-fifo-size for USB DWC2 driver - Fix trusted STM32MP1 defconfig with correct ethernet driver
2019-06-20t2080: dts: Added PCIe DT nodesHou Zhiqiang
T2080 integrated 4 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 3.0, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-20powerpc: mpc85xx: Update the condition to compile PCI routinesHou Zhiqiang
Compile the routines of mpc85xx/pci.c when both FSL_PCI_INIT and DM_PCI are not enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-20powerpc: mpc85xx: Move CONFIG_FSL_PCIE_RESET to KconfigHou Zhiqiang
Use the Kconfig option to select the PCIe reset errata. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-20powerpc: mpc85xx: Move CONFIG_FSL_PCIE_DISABLE_ASPM to KconfigHou Zhiqiang
Use the Kconfig option to select the PCIe ASPM errata. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini
- LS1046AFRWY support - USB errata fix and secure boot defconfig support for LS1028A - Enabled SDHC and SATA for LX2160 - LS1046A serdes fixes - other minor fixes
2019-06-19ARM: dts: stm32mp1: remove override for g-tx-fifo-sizePatrick Delaunay
Remove the override for usbotg_hs on g-tx-fifo-size as the correct binding, used in the kernel device tree, is now supported in dwc2 device driver. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-06-19armv8: ls1046afrwy: Add support for LS1046AFRWY platformVabhav Sharma
LS1046AFRWY board supports LS1046A family SoCs. This patch add base support for this board. Board support's 4GB ddr memory, i2c, micro-click module,microSD card, serial console,qspi nor flash,ifc nand flash,qsgmii network interface, usb 3.0 and serdes interface to support two x1gen3 pcie interface. Signed-off-by: Camelia Groza <camelia.groza@nxp.com> Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19arm: ls1028a: define the integrated PCI bus (ECAM)Alex Marginean
LS1028A includes an integrated PCI bus with 11 PCI functions residing on bus 0. ECAM plus the device register space takes up 256MB of address space. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: fsl-lsch2: add clock support for the second eSDHCYinbo Zhu
Layerscape began to use two eSDHC controllers, for example, LS1012A. They are same IP block with same reference clock. This patch is to add clock support for the second eSDHC. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19arm: fsl-layerscape: add 0x3040 serdes1 settings for LS1046AMaciej Pijanowski
Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Cc: piotr.krol@3mdeb.com Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19arm: fsl-layerscape: fix 0x3363 serdes1 settings for ls1046aMaciej Pijanowski
As per LS1046A hardware manual, SGMII.9 and SGMII.10 present on lane D and lane C respectively for 0x3363 protocol. So fix serdes1 settings for ls1046a. Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
generated by cgit (git 2.34.1) at 2024-12-27 21:56:12 +0000