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2011-07-14imx: Use correct imx25 reset.cMatthias Weisser
imx25 used the wrong reset.c from imx27 Signed-off-by: Matthias Weisser <weisserm@arcor.de>
2011-07-14imx: Add get_tbclk() function for imx25Matthias Weisser
Need this function for autoboot keyd Signed-off-by: Matthias Weisser <weisserm@arcor.de>
2011-07-14mx27: Make the UART port number explicitFabio Estevam
mx27_uart_init_pins does the IOMUX setting for UART1 port. Change the function name to make the UART port number explicit. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-07-14build: Add targets for auto gen of asm-offsets.h and use it in imx35Matthias Weisser
asm-offsets.h should be auto generated. This patch adds two rules to rules.mk which makes this possible and removes the rules on imx35. Signed-off-by: Matthias Weisser <weisserm@arcor.de> Acked-by: Stefano Babic <sbabic@denx.de>
2011-07-11powerpc/85xx: remove SERDES4 soft-reset work-aroundTimur Tabi
Some P4080 rev1 errata work-arounds, notably erratum SERDES4, required a bank soft-reset after the bank was configured and enabled, even though enabling a bank causes it to reset. Because the reset was required for multiple errata, it was not properly enclosed in an #ifdef, and so was not removed with all the other rev1 errata work-arounds. Erratum SERDES-8 says that the clocks for bank 3 needs to be enabled if bank 2 is enabled, but this was not being done for SERDES protocols 0xF and 0x10. The bank reset also happened to enable bank 3 (apparently an undocumented feature). Simply removing the reset breaks these two protocols. It turns out that every time we call enable_bank(), we do want at least one lane of the bank enabled, either because the bank is supposed to be enabled, or because we need the clock from that bank enabled. For erratum SERDES-A001, we don't want to modify srds_lpd_b[] when we call enable_bank(), because that array is used elsewhere to determine if the bank is available. Note that the side effect of these changes is that the work-arounds for these two errata are now linked. Specifically, if SERDES-A001 is enabled, then we need SERDES-8 enabled as well. Because this was the only SERDES bank soft-reset, there is no need to implement a work-around for erratum SERDES-A003. Also fix an off-by-one error in a printf(). Signed-off-by: Timur Tabi <timur@freescale.com> Acked-by: Ed Swarthout <swarthou@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11powerpc/mpc8xxx: Allow override DDR read-to-write turnaround timeYork Sun
Add this option to allow boards to override the default read-to-write turnaround time for better performance. Signed-off-by: York Sun <yorksun@freescale.com>
2011-07-11powerpc/8xxx: Update USB mode device tree fixupRamneek Mehresh
Modify support for USB mode fixup: - Add common support for USB mode and phy type device tree fix-up for all USB controllers mentioned in hwconfig string - Fetch USB mode and phy type via hwconfig; if not defined in hwconfig, then fetch them from env Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11powerpc/mpc8xxx: fix DDR data width checkingYork Sun
Checking width before setting DDR controller. SPD for DDR1 and DDR2 has data width and primary sdram width. The latter one has different meaning for DDR3. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11powerpc/mpc8xxx: Adding fallback to raw timing on supported boardsYork Sun
In case of empty SPD or checksum error, fallback to raw timing on supported boards. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11powerpc/mpc8xxx: Enable calculation for fixed DDR chipsYork Sun
We used to have fixed parameters for soldered DDR chips. This patch introduces CONFIG_SYS_DDR_RAW_TIMING to enable calculation based on timing data from DDR chip datasheet, implemneted in board-specific files or header files. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11powerpc/85xx: Fix pin muxing for second USB controllerFelix Radensky
On P1022/P1013 second USB controller is muxed with second Ethernet controller. The current code to enable second USB fails to properly clear pinmux bits used by ethernet. As a result, Linux freezes when this controller is used. This patch fixes the problem. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11powerpc/mpc8xxx: Add 16-bit support for DDR3York Sun
Add support for 16-bit DDR bus. Also deal with system using 64- and 32-bit DDR devices. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11powerpc/mpc8xxx: check SPD length before using part numberYork Sun
Only use DDR DIMM part number if SPD has valid length, to prevent from display garbage in case SPD doesn't cover these fields. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11powerpc/mpc8xxx: adjust DDR burst length and chop accroding to sdram widthYork Sun
If the bus width is 32-bit, burst chop should be disabled and burst length should be 8. Read from SPD or other source to determine the width. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11powerpc/85xx: Add P2041 processor supportKumar Gala
The P2041 is similar to P2040, however has a 10G port and backside L2 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11powerpc/p2040: Add various p2040 specific informationMingkai Hu
Add P2040 SoC specific information: * LIODN setup * Portal configuration * etc Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11powerpc/85xx: Fix compile errors if CONFIG_SYS_DPAA_QBMAN isn't setKumar Gala
Add ifdef protection for qp_info and liodn associated with Q/BMan. Also rearrange setting of _tbl_sz variables to utilize existing ifdef protection for things like FMAN. Also add protection around setup_portals() call in corenet_ds board code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11powerpc/85xx: Fix compile errors if CONFIG_SYS_{BR,OR}0_PRELIM aren't setKumar Gala
Add ifdef protection in LBC code to handle the case in which CONFIG_SYS_BR0_PRELIM and CONFIG_SYS_OR0_PRELIM arent defined for a build. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-06MPC83XX: Fix PCI express clock setupBill Cook
On a 8308 based board it was found that the PEX_GLK_RATIO register (programmed in arch/powerpc/cpu/mpc83xx/pcie.c) was getting set to 0, This was tracked to the fact that the pci express clock frequency was not being assigned to the pciexp1_clk entry in the global data structure in file arch/powerpc/cpu/mpc83xx/speed.c. Fix this and a similiar issue in 'do_clocks' command. Signed-off-by: Bill Cook <cook@isgchips.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2011-07-06MPC83xx: add config options for memory setup.Andre Schwarz
CPO value and driver strength settings are board specifc. Also allow SPD data fetch from any accessible I2C EEPROM. Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Acked-by: York Sun <yorksun@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2011-07-06MPC837x: set i2c1_clkAndre Schwarz
Running on mpc837x without CONFIG_FSL_ESDHC leads to i2c1_clk not being set at all. It is bound to clock of encryption module. fix this. Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2011-07-04arm/kirkwood: if CONFIG_SOFT_I2C is set don't set CONFIG_I2C_MVTWSIHolger Brunck
Some boards e.g. keymile arm boards have CONFIG_CMD_I2C switched on but they use soft i2c on kirkwood. So don't switch CONFIG_I2C_MVTWSI on in this case. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> cc: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> cc: Heiko Schocher <hs@denx.de>
2011-07-04Fix compiler error for cpu at91sam9, if lowlevel init is enabledJens Scharsig
* Fix compiler error for cpu at91sam9, if lowlevel init is enabled * use correct ATMEL_ name scheme to define ATMEL_BASE_SDRAMC Signed-off-by: Jens Scharsig
2011-07-04arm920t/at91: add at91rm9200_devices.cAndreas Bießmann
This is a copy of arm926ejs/at91 api for perpherial initialisation. At the moment we just need the usart part of the api. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2011-07-04arm920t/at91: use new clock.c featuresAndreas Bießmann
This patch enables the new clock features from arm920t/at91/clock.c. This is an required step to get at91rm9200_usart replaced by atmel_usart driver. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Jens Scharsig <js_at_ng@scharsoft.de> Cc: Eric Bénard <eric@eukrea.com>
2011-07-04arm920t/at91: add clock.cAndreas Bießmann
This patch adds an copy of arm926ejs/at91/clock.c to arm920t/at91. The arm926ejs specialities are removed from arm920t version and vice versa. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2011-07-04at91rm9200.h: fix ATMEL_PMX_AA_TXD2Andreas Bießmann
This patch sets the ATMEL_PMX_AA_TXD2 to the correct value. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> CC: Jens Scharsig <js_at_ng@scharsoft.de> CC: eric@eukrea.com Acked-by: Eric Bénard <eric@eukrea.com>
2011-07-04MX5: Introduce a function for setting the chip select sizeFabio Estevam
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-07-04MX5: Add iomux structureFabio Estevam
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-07-04MX5: Make the weim structure completeFabio Estevam
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-07-04OMAP[34]: fix broken timerJohn Rigby
As implemented now the timer used to implement __udelay counts to 0xffffffff and then gets stuck there because the the programmed reload value is 0xffffffff. This value is not only wrong but illegal according to the reference manual. One can reproduce the bug by leaving a board at the u-boot prompt for sometime then issuing a sleep command. The sleep will hang forever. The timer is a count up timer that reloads as it rolls over from 0xffffffff so the correct load value is 0. Change TIMER_LOAD_VAL from 0xffffffff to 0 and introduce a new constant called TIMER_OVERFLOW_VAL set to 0xffffffff. Signed-off-by: John Rigby <john.rigby@linaro.org> Tested-by: Igor Grinberg <grinberg@compulab.co.il>
2011-07-04GPIO: Tegra2: add GPIO driver for Tegra2Tom Warren
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-07-04armv7: adapt s5pc1xx to the new cache maintenance frameworkAneesh V
adapt s5pc1xx to the new layered cache maintenance framework Signed-off-by: Aneesh V <aneesh@ti.com>
2011-07-04armv7: adapt omap3 to the new cache maintenance frameworkAneesh V
adapt omap3 to the new layered cache maintenance framework Signed-off-by: Aneesh V <aneesh@ti.com>
2011-07-04armv7: adapt omap4 to the new cache maintenance frameworkAneesh V
adapt omap4 to the new layered cache maintenance framework Signed-off-by: Aneesh V <aneesh@ti.com>
2011-07-04armv7: add PL310 support to u-bootAneesh V
PL310 is the L2$ controller from ARM used in many SoCs including the Cortex-A9 based OMAP4430 Add support for some of the key PL310 operations - Invalidate all - Invalidate range - Flush(clean & invalidate) all - Flush range Signed-off-by: Aneesh V <aneesh@ti.com>
2011-07-04arm: minor fixes for cache and mmu handlingAneesh V
1. make sure that page table setup is not done multiple times 2. flush_dcache_all() is more appropriate while disabling cache than a range flush on the entire memory(flush_cache()) Provide a default implementation for flush_dcache_all() for backward compatibility and to avoid build issues. Signed-off-by: Aneesh V <aneesh@ti.com>
2011-07-04armv7: integrate cache maintenance supportAneesh V
- Enable I-cache on bootup - Enable MMU and D-cache immediately after relocation - Do necessary initialization before enabling d-cache and MMU - Changes to cleanup_before_linux() - Make changes according to the new framework Signed-off-by: Aneesh V <aneesh@ti.com>
2011-07-04armv7: rename cache related CONFIG flagsAneesh V
Replace the cache related CONFIG flags with more meaningful names. Following are the changes: CONFIG_L2_OFF -> CONFIG_SYS_L2CACHE_OFF CONFIG_SYS_NO_ICACHE -> CONFIG_SYS_ICACHE_OFF CONFIG_SYS_NO_DCACHE -> CONFIG_SYS_DCACHE_OFF Signed-off-by: Aneesh V <aneesh@ti.com> V2: * Changed CONFIG_L2_OFF -> CONFIG_SYS_NO_L2CACHE V4: * Changed all three flags to the final names suggested as above and accordingly changed the commit message
2011-07-04armv7: cache maintenance operations for armv7Aneesh V
- Add a framework for layered cache maintenance - separate out SOC specific outer cache maintenance from maintenance of caches known to CPU - Add generic ARMv7 cache maintenance operations that affect all caches known to ARMv7 CPUs. For instance in Cortex-A8 these opertions will affect both L1 and L2 caches. In Cortex-A9 these will affect only L1 cache - D-cache operations supported: - Invalidate entire D-cache - Invalidate D-cache range - Flush(clean & invalidate) entire D-cache - Flush D-cache range - I-cache operations supported: - Invalidate entire I-cache - Add maintenance functions for TLB, branch predictor array etc. - Enable -march=armv7-a so that armv7 assembly instructions can be used Signed-off-by: Aneesh V <aneesh@ti.com>
2011-07-04arm: make default implementation of cache_flush() weakly linkedAneesh V
make default implementation of cache_flush() weakly linked so that sub-architectures can override it Signed-off-by: Aneesh V <aneesh@ti.com>
2011-06-27Minor coding style fixes.Wolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-06-23Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk
* 'master' of git://git.denx.de/u-boot-arm: run arm_pci_init after relocation IXP42x PCI rewrite update/fix PDNB3 board update/fix IXDP425 / IXDPG425 boards add dvlhost (dLAN 200 AV Wireless G) board IXP NPE: add support for fixed-speed MII ports update/fix AcTux4 board update/fix AcTux3 board update/fix AcTux2 board update/fix AcTux1 board use -ffunction-sections / --gc-sections on IXP42x support CONFIG_SYS_LDSCRIPT on ARM fix "depend" target in npe directory Fix IXP code to work after relocation was added trigger hardware watchdog in IXP42x serial driver add support for IXP42x Rev. B1 and newer add XScale sub architecture (IXP/PXA) to maintainer list Conflicts: arch/arm/lib/board.c Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-06-23run arm_pci_init after relocationMichael Schwingen
Signed-off-by: Michael Schwingen <michael@schwingen.org>
2011-06-23IXP42x PCI rewriteMichael Schwingen
clean up IXP PCI handling: get rid of IXP-private bus scan, BAR assign etc. code and use u-boot's PCI infrastructure instead. Move board-specific PCI setup code (clock/reset) to board directory. Signed-off-by: Michael Schwingen <michael@schwingen.org>
2011-06-23IXP NPE: add support for fixed-speed MII portsMichael Schwingen
Signed-off-by: Michael Schwingen <michael@schwingen.org>
2011-06-23use -ffunction-sections / --gc-sections on IXP42xMichael Schwingen
Signed-off-by: Michael Schwingen <michael@schwingen.org>
2011-06-23support CONFIG_SYS_LDSCRIPT on ARMMichael Schwingen
Signed-off-by: Michael Schwingen <michael@schwingen.org>
2011-06-23fix "depend" target in npe directoryMichael Schwingen
Signed-off-by: Michael Schwingen <michael@schwingen.org>
2011-06-23Fix IXP code to work after relocation was addedMichael Schwingen
- jump to real flash location after reset before turning off flash mirror - fix timer system to use HZ == 1000, remove broken interrupt-based code Signed-off-by: Michael Schwingen <michael@schwingen.org>
generated by cgit (git 2.34.1) at 2024-12-27 04:38:13 +0000