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Use CCTL command to do d-cache write back
and invalidate instead of fence.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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When L2 node exists inside cpus node, uclass_get_device
can not parse L2 node successfully. So move it outside
from cpus node.
Also add tag-ram-ctl and data-ram-ctl attributes for
v5l2 cache controller driver. This can adjust timing
by requirement from dtb to improve performance.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Flush and disable L2 cache in dcache_disable()
which will be called in cleanup_before_linux()
before jump to linux.
The sequence will be preferred as below:
L1 flush -> L1 disable -> L2 flush -> L2 disable
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Select the v5l2 UCLASS_CACHE driver for ax25.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Initialize plic driver by ofnode_for_each_subnode() instead
of cpu_get_count().
This way can support to skip some harts which maybe marked as
unavailable, but the cpu node exists indeed.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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The addend is now added for RELOC_TYPE relocs. Also, changed the loop
structure so that all the R_RISCV_RELATIVE relocs are not required to
be at the beginning of the list.
Signed-off-by: Marcus Comstedt <marcus@mc.pp.se>
Cc: Rick Chen <rick@andestech.com>
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Add DT entry for the DM PCI driver, update board configs
and drop ad-hoc board init code for the PCI bus. Instead,
let the DM PCI driver initialize and operate the hardware.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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Enable OF control for SH4 R2Dplus board. This is necessary, because
the PCI uclass is designed in a way that makes it depend on DT and
disallows instanciating devices without DT (e.g. with platdata).
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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If the OF_SEPARATE is enabled, the DT is appended past the _end symbol.
The current code however clears BSS very early, which overwrites the DT
blob with zeroes. Moreover, the early code relocates U-Boot into RAM to
the correct location, but does not relocate the DT.
This patch adds code to relocate the DT and avoids clearing BSS too
early, thus addressing both problems with OF_SEPARATE on SH.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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Fix the offset of TCNT0 register, which is 0xc on SH4.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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When CONFIG_CLK enabled, use CLK UCLASS for clk related settings.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
hs: removed hunk in mxc_i2c_probe() as not longer in code
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- r8a66597 usb changes
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This reverts commit fc04b923541d984b1544056fd3bfa8129d4e5aac where the
FVP DRAM configuration was added.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
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The current code in reserve_noncached() has two issues:
1) The first update of gd->start_addr_sp always rounds down to a section
start. However, the equivalent calculation in cache.c:noncached_init()
always first rounds up to a section start, then subtracts a section size.
These two calculations differ if the initial value is already rounded to
section alignment.
2) The second update of gd->start_addr_sp subtracts exactly
CONFIG_SYS_NONCACHED_MEMORY, whereas the equivalent calculation in
cache.c:noncached_init() rounds the noncached size up to section
alignment before subtracting it. The two calculations differ if the
noncached region size is not a multiple of the MMU section size.
In practice, one/both of those issues causes a practical problem on
Jetson TX1; U-Boot triggers a synchronous abort during initialization,
likely due to overlapping use of some memory region.
This change fixes both these issues by duplicating the exact calculations
from noncached_init() into reserve_noncached().
However, this fix assumes that gd->start_addr_sp on entry to
reserve_noncached() exactly matches mem_malloc_start on entry to
noncached_init(). I haven't traced the code to see whether it absolutely
guarantees this in all (or indeed any!) cases. Consequently, I added some
comments in the hope that this condition will continue to be true.
Fixes: 5f7adb5b1c02 ("board_f: reserve noncached space below malloc area")
Cc: Vikas Manocha <vikas.manocha@st.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Enable DM PCI for T2080RDB, T4240RDB, T1024RDB, T1042D4RDB, P1020RDB,
P2020RDB, P2041RDB, P3041DS, P4080DS, and MPC8548CDS
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MPC8548 integrated a PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 1.0a, and this
patch is to add DT node for the PCIe controller.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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P5040 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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P4080 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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P3041 integrated 4 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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P2041 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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P2020 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 1.0a, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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P1020 integrated 2 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 1.0a, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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T104x integrated 4 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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T102x integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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T4240 integrated 4 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 3.0, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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https://gitlab.denx.de/u-boot/custodians/u-boot-stm
- Fixes and update related to STM32MP1 platforms
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Support of device tree model for T2080RDB, T4240RDB, T1024RDB,
T1042D4RDB, P1020RDB, P2020RDB, P2041RDB, P3041DS, P4080DS, P5040DS and
MPC8548CDS. Also support of i2c dm model.
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Alignment with kernel patch proposal for binding:
[PATCH v4 0/8] stm32 m4 remoteproc on STM32MP157c
https://lkml.org/lkml/2019/5/14/159
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
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Since the commit 8729b1ae2cbd ("misc: Update read() and
write() methods to return bytes xfered"); The misc bsec driver
need to be adapted to reflect the number of transferred bytes.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
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Don't compile psci for SPL build.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
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Due to kernel DT alignment, pwr-supply is renamed to vdd-supply
and is a subnode of pwr-regulators.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
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Create a function led_error_blink and add node in device
tree.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
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As for Audio codec IC, HDMI IC is not "IO safe".
HDMI regulators (v3v3 and v1v2) must be enabled to allow
I2C1 bus usage. HDMI IC must be under reset during power up
and keep HDMI and AUDIO devices in reset while they are not
used in U-Boot to keep them in low power mode
(each device can be kept in reset independently keeping their
power supplies ON until kernel).
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
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Add the boot for NOR, SPL load U-Boot.img at offset
CONFIG_SYS_SPI_U_BOOT_OFFS = 0x80000.
It is the start address of mtd partition ssbl in nor.
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
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Only activate WATCHDOG in SPL when CONFIG_WATCHDOG is activated in U-Boot.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
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Add imply for FDT overlay that can be usefuill for kernel device tree
management but it is not mandatory (can be removed to gain space)
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
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Activate DISABLE_CONSOLE needed for stm32prog support on uart.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
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Select the serial driver mandatory for the console.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
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Correctly handle silent=1 in the default environment.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
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Allow to disable console with environment variable 'silent':
> env set silent 1; env save
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
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Depending on backup register value, we maintain the debug unit
powered-on for debugging purpose.
Only BUCK1 is required for powering the debug unit, so revert
the setting for all the other power lanes, except BUCK3 that
has to be always on.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
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Avoid U-Boot auto-boot interruption for line break detection
on console when the RX line connected to STLINK is floating
(-IO error in getc cause by framing error and testc return 1)
Same workaround is applied on all the STMicroelectonics board.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
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Allow to use PA13 and PA14 to force fastboot mode or STM32CubeProgrammer
mode.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
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The pre-relocation probe is needed to reserve video frame buffer
in video_reserve() for all the board;
LDTC must be tagged prereloc in SOC U-Boot dtsi file.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
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Add node in DT and avoid error to search UCLASS_SYSRESET in
board_f.c::print_resetinfo() and lost 1.6s in U-Boot
for the trusted boot chain.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
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This patch adds independent watchdog support for stm32mp157c
in SPL.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
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Update DDR configuration with the latest update:
- Change DQSGE to 1 for DDR3, to cure missing DQS preamble.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
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Synchronize device tree with v5.3-rc2 label and
update the associated u-boot dtsi.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
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Synchronize U-boot DT with kernel v5.2 for stih410-b2260.
Update stih410-b2260-u-boot.dtsi accordingly.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
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- Assorted minor bugfixes
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