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2020-07-22arm: dts: rockchip: Sync rk3288 dtsi from linuxSuniel Mahesh
This sync has changes required to use HDMI CEC pin in U-Boot. Sync dts from linux v5.8-rc5 commit: "ARM: dts: rockchip: define the two possible rk3288 CEC pins" (sha1: 838980dd04e994bf81cf104fa01ae60802146b39) Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-07-22ARM: dts: rockchip: Sync ROCKPi N8/N10 dts(i) from LinuxJagan Teki
Sync ROCKPi N8/N10 dts(i) changes from Linux. commit <afd9eb880414> ("ARM: dts: rockchip: Add Radxa Rock Pi N8 initial support") Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-07-22rockchip: Separate the reset cause from display cpuinfoJagan Teki
reset cause is a generic functionality based on the soc cru registers in rockchip. This can be used for printing the cause of reset in cpuinfo or some other place where reset cause is needed.  Other than cpuinfo, reset cause can also be using during bootcount for checking the specific reset cause and glow the led based on the reset cause. So, let's separate the reset cause code from cpuinfo, and add a check to build it for rk3399, rk3288 since these two soc are supporting reset cause as of now. Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22rockchip: Don't clear the reset status regJagan Teki
reset reason can be used several stages of U-Boot bootloader like SPL, U-Boot proper based on the requirements. Clearing the status register end of get_reset_cause will end up showing the wrong reset cause when it read the second time. For example, if board resets, SPL reads the reset status as RST whereas U-Boot proper reads the status as POR. However, based on the latest testing clearing reset status won't be required for determine the last reset cause or following resets. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22rockchip: tpl: Remove board_early_init_f()Kever Yang
There is no need for board_early_init_f() in TPL, anything like this should goes to SPL. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22rockchip: rk3399: Add weak led_setup()Jagan Teki
Add weak led_setup() so that board which has an uncommon led setup code that can make use of custom implementation. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22rockchip: rk3288: Add OF board setupJagan Teki
The new rk3288 revision rk3288w has some changes with respect to legacy rk3288 like hclk_vio in cru and usb host0 ohci. Linux clock driver already handle this via rockchip,rk3288w-cru compatible. USB ohci host can enable via dts for rk3288w based boards. So, add fdt board setup code to update cru compatible with rk3288w-cru compatible if the SOC revision is RK3288W. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22rockchip: Add rk3288 SoC detection helperJagan Teki
Rockchip SoC's has a new revision chip for rk3288 SoCs. RK3288 has a new revision chip called RK3288W which is similar but different hclk_vio clock and fixed OHCI host. Add common Rockchip SoC detection helper to support this rk3288w detection. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22arm64: dts: rockchip: Add Radxa ROCK Pi 4C supportJagan Teki
Rock PI 4C has AP6256 Wifi/BT, PoE, miniDP, USB Host enabled GPIO pin change compared to 4B, 4C. So, add or enable difference nodes/properties in 4C dts by including common dtsi. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22arm64: dts: rockchip: Add ROCKPi 4A/4B supportJagan Teki
Rock PI 4 has 3 variants of hardware platforms called RockPI 4A, 4B, and 4C. - Rock PI 4A has no Wif/BT. - Rock PI 4B has AP6256 Wifi/BT, PoE. - Rock PI 4C has AP6256 Wifi/BT, PoE, miniDP, USB Host enable GPIO pin change compared to 4B, 4C So move common nodes, properties into dtsi file and include on respective variant dts files. Use 4B dts into default rock-pi-4 defconfig until we find any solution for dynamic detection of these variants. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22rockchip: sdram: fix dram_init_banksizeAlex Bee
Currently 2.5 GB is calculated as DRAM size for a 1 GB RK322x board if CONFIG_SPL_OPTEE is set. This is troublesome when booting a linux kernel since this size will be injected in FDT of the kernel. gd->bd->bi_dram[0].start (which is basically CONFIG_SYS_SDRAM_BASE) must not be taken into consideration for calculation of second bank size, since this offset is already included in calculation of "top". After applying this patch 992 MB (1024 MB - 32 MB reserved for optee-os) is correctly calculated and has also been verified on 2 GB boards. Signed-off-by: Alex Bee <knaerzche@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22rockchip: ram: fix debug funcfion define when RAM_ROCKCHIP_DEBUG not setKever Yang
The empty function define should not be in the header file, or else the build will error with function multi definition after CONFIG_RAM_ROCKCHIP_DEBUG is disabled. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22ARM: dts: rk3328-rock64: Add SPI Flash supportJohannes Krottmayer
Add U-Boot SPI Flash support for the PINE64 Rock64 board Signed-off-by: Johannes Krottmayer <krjdev@gmail.com> Cc: Matwey V. Kornilov <matwey.kornilov@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22ARM: dts: rk3328: Add SPI supportJohannes Krottmayer
Add U-Boot SPI support for the RK3328 Signed-off-by: Johannes Krottmayer <krjdev@gmail.com> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> (fix checkpatch error for code ident) Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22rockchip: board: add Hardkernel Odroid Go2 boardHeiko Stuebner
Also known as Odroid Go Advance but named Go2 internally by the vendor it seems. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22rockchip: px30: sync Odroid Go Advance devicetree from LinuxHeiko Stuebner
Get the devicetree from mainline Linux and include it for U-Boot uses. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22rockchip: px30: sync the main rk3326 dtsi from mainlineHeiko Stuebner
The rk3326 is just a trimmed down px30 from a software perspective, so the mainline rk3326 dtsi also ist just a tiny addition. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-20treewide: convert devfdt_get_addr() to dev_read_addr()Masahiro Yamada
When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-20arm: mach-k3: Use SOC driver for device identificationDave Gerlach
Make use of UCLASS_SOC to find device family and revision for print_cpuinfo. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2020-07-20arm: dts: k3-j721e-mcu-wakeup: Introduce chipid nodeDave Gerlach
Introduce a chipid node to provide a UCLASS_SOC driver to identify TI K3 SoCs. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2020-07-20arm: dts: k3-am65-wakeup: Introduce chipid nodeDave Gerlach
Introduce a chipid node to provide a UCLASS_SOC driver to identify TI K3 SoCs. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2020-07-20test: Add tests for SOC uclassDave Gerlach
Add a sandbox SOC driver, and some tests for the SOC uclass. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2020-07-20cpu: Convert the methods to use a const udevice *Simon Glass
These functions should not modify the device. Convert them to const so that callers don't need to cast if they have a const udevice *. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-20x86: mp: Add more comments to the moduleSimon Glass
Add a description of how this module works and also some missing function comments. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20x86: mtrr: Add support for writing to MTRRs on any CPUSimon Glass
To enable support for the 'mtrr' command, add a way to perform MTRR operations on selected CPUs. This works by setting up a little 'operation' structure and sending it around the CPUs for action. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-20x86: mtrr: Update MTRRs on all CPUsSimon Glass
When the boot CPU MTRRs are updated, perform the same update on all other CPUs so they are kept in sync. This avoids kernel warnings about mismatched MTRRs. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20x86: Don't enable SMP in SPLSimon Glass
SMP should be set up in U-Boot where possible, not SPL. Disable it in SPL. For 64-bit U-Boot we should find a way to allow SMP operations in U-Boot, but this is somewhat more complicated. For now that is disabled too. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-20x86: mtrr: Use MP calls to list the MTRRsSimon Glass
Update the mtrr command to use mp_run_on_cpus() to obtain its information. Since the selected CPU is the boot CPU this does not change the result, but it sets the stage for supporting other CPUs. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20x86: mp: Add iterators for CPUsSimon Glass
It is convenient to iterate through the CPUs performing work on each one and processing the result. Add a few iterator functions which handle this. These can be used by any client code. It can call mp_run_on_cpus() on each CPU that is returned, handling them one at a time. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20x86: mp: Park CPUs before running the OSSimon Glass
With the new MP features the CPUs are no-longer parked when the OS is run. Fix this by calling a special function to park them, just before the OS is started. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20x86: mp: Allow running functions on multiple CPUsSimon Glass
Add a way to run a function on a selection of CPUs. This supports either a single CPU, all CPUs, just the main CPU or just the 'APs', in Intel terminology. It works by writing into a mailbox and then waiting for the CPUs to notice it, take action and indicate they are done. When SMP is not yet enabled, this just calls the function on the main CPU. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20x86: Set the SMP flag when MP init is completeSimon Glass
Set this flag so we can track when it is safe to use CPUs other than the main one. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20x86: mp: Support APs waiting for instructionsSimon Glass
At present the APs (non-boot CPUs) are inited once and then parked ready for the OS to use them. However in some cases we want to send new requests through, such as to change MTRRs and keep them consistent across CPUs. Change the last state of the flight plan to go into a wait loop, accepting instructions from the main CPU. Drop cpu_map since it is not used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20x86: cpu: Remove unnecessary #ifdefsSimon Glass
Drop some #ifdefs that are not needed or can be converted to compile-time checks. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20x86: mp_init: Adjust bsp_init() to return more informationSimon Glass
This function is misnamed since it does not actually init the BSP. Also it is convenient to adjust it to return a little more information. Rename and update the function, to allow it to return the BSP CPU device and number, as well as the total number of CPUs. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20x86: mp_init: Set up the CPU numbers at the startSimon Glass
At present each CPU is given a number when it starts itself up. While this saves a tiny amount of time by doing the device-tree read in parallel, it is confusing that the numbering happens on the fly. Move this code into mp_init() and do it at the start. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20x86: mp_init: Drop the num_cpus static variableSimon Glass
This does not need to be global across all functions in this file. Pass a parameter instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20x86: mp_init: Switch parameter names in start_aps()Simon Glass
These parameters are named differently from elsewhere in this file. Switch them to avoid confusion. Also add comments to this function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-20x86: mp_init: Avoid declarations in header filesSimon Glass
The functions used by the flight plan are declared in the header file but are not used in any other file. Move the flight plan steps down to just above where it is used so that we can make these function static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20x86: Move MP code into mp_initSimon Glass
At present the 'flight plan' for CPUs is passed into mp_init. But it is always the same. Move it into the mp_init file so everything is in one place. Also drop the SMI function since it does nothing. If we implement SMIs, more refactoring will be needed anyway. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20x86: mp_init: Switch to livetreeSimon Glass
Update this code to use livetree calls instead of flat-tree. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-18mips: octeon: Add minimal Octeon 3 EBB7304 EVK supportStefan Roese
This patch adds very basic minimal support for the Marvell Octeon 3 CN73xx based EBB7304 EVK. Please note that the basic Octeon port does not support DDR3/4 initialization yet. To still use U-Boot on with this port, the L2 cache (4MiB) is used as RAM. This way, U-Boot can boot to the prompt on this board. Supported devices: - UART - reset - CFI parallel NOR flash Signed-off-by: Stefan Roese <sr@denx.de>
2020-07-18mips: octeon: use mips_mach_early_init() to copy to L2 cacheStefan Roese
This patch adds the code to copy itself from bootrom location to a different location (TEXT_BASE) to the Octeon platform. Its used in this case to copy the complete U-Boot image into L2 cache, which greatly improves the bootup time - especially in regard to the very long and complex DDR4 init code. The Kconfig symbol CONFIG_MIPS_MACH_EARLY_INIT is enabled with this patch for Octeon. Signed-off-by: Stefan Roese <sr@denx.de>
2020-07-18mips: octeon: dts: Add Octeon 3 cn73xx base dtsi fileStefan Roese
This patch adds the base dtsi file for the Octeon 3 cn73xx SoC. Signed-off-by: Stefan Roese <sr@denx.de>
2020-07-18mips: octeon: Initial minimal support for the Marvell Octeon SoCAaron Williams
This patch adds very basic support for the Octeon III SoCs. Only CFI parallel NOR flash and UART is supported for now. Please note that the basic Octeon port does not include the DDR3/4 initialization yet. This will be added in some follow-up patches later. To still use U-Boot on with this port, the L2 cache (4MiB on Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the prompt on such boards. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2020-07-18mips: Add CONFIG_MIPS_MACH_EARLY_INIT for very early mach init codeStefan Roese
This patch adds the optional call to mips_mach_early_init() to start.S at a very early stage. Its disabled per default. It can be used for very early machine / platform specific init code. Its called very early and at this stage the PC is allowed to differ from the linking address (CONFIG_TEXT_BASE) as no absolute jump has been performed until this call. It will be used by thje Octeon platform. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2020-07-18mips: sync asm/mipsregs.h with Linux 5.7Daniel Schwierzeck
Sync asm/mipsregs.h with Linux 5.7. Also replace the custom symbols EBASE_CPUNUM and EBASE_WG with the according symbols from Linux. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2020-07-18mips: sync asm/addrspace.h with Linux 5.7Daniel Schwierzeck
Sync asm/addrspace.h with Linux 5.7 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2020-07-18mips: sync asm/asm.h with Linux 5.7Daniel Schwierzeck
Sync asm/asm.h with Linux 5.7. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2020-07-18mips: remove deprecated UNCACHED_SDRAM() macroDaniel Schwierzeck
This macro only served as a wrapper for CKSEG1ADDR() with an exception for CONFIG_TB0229. CONFIG_TB0229 doesn't exist, thus use CKSEG1ADDR() directly. This also prepares for an upcoming asm header sync with Linux. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
generated by cgit (git 2.34.1) at 2024-12-25 01:34:34 +0000