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2018-05-28sunxi: clock: Fix OHCI clock gating for H3/H5Chen-Yu Tsai
Clock gating bits on H43/H5 were wrong, fix them. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28sunxi: clock: Fix clock gating for H3/H5/A64Jagan Teki
clock gating bits on a64 are different than H3_H5, so fixed only required bits on clock_sun6i.h. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-25Revert "sunxi: binman: Add U-Boot binary size check"Maxime Ripard
This reverts commit 819f1e081c527d2d02cdaeec0027384688cf5de0. This check was introduced in order to cope with the size limitation we had when we were still using the raw environment in MMC. However, this introduces padding as well, which can result in an overly huge binary if one wants to flash the environment to some other location. Since we now have a FAT-based environment, this check is not so useful anymore, so we can just drop it. Cc: Andre Przywara <andre.przywara@arm.com> Cc: Måns Rullgård <mans@mansr.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-05-24ARC: init debug uart in early common arc codeEugeniy Paltsev
The debug UART is intended for use very early in U-Boot to debug problems before serial drivers are up. Call debug_uart_init right before board_init_f. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-05-23arm: print instructions pointed to by pcHeinrich Schuchardt
If an exception occurs in a loaded image and the relocation offset is unknown, it is helful to know the instructions pointed to by the program counter. This patch adds the missing output. A possible output is: Code: e1c560d0 e12fff1e e120077b e12fff1e (e7f7defb) The parentheses indicate the instruction causing the exception. The output can be disassembled using the decodecode script provided by the Linux kernel project. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2018-05-23arm64: timer: Create timer_get_bootus for bootstage supportMichal Simek
Implement timer_get_boot_us() based on available functions to support bootstage command. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-23arm: armv7m: Clean up some thumb / compiler flag optionsTom Rini
- The correct way to build with thumb mode is to select SYS_THUMB_BUILD - We should be setting -march=armv7-m in arch/arm/Makefile not the sub-config.mk file. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-22at91: Minor tweaks to SPL logic for space savings on smartwebTom Rini
- spl_board_init is empty on smartweb so drop that function - When CONFIG_AT91SAM9_WATCHDOG is set we do not disable the watchdog in SPL and instead let full U-Boot handle it. Instead of an empty function just do not call a function. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-23ARM: dts: uniphier: sync with Linux 4.17-rc6Masahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-05-23ARM: uniphier: rename environment variable fdt_file to fdtfileMasahiro Yamada
For booting Linux in the generic distro mechanism, cmd/pxe.c retrieves the FDT file name from "fdtfile" environment variable. Rename "fdt_file" to "fdtfile" for easier migration to distro boot. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-05-23ARM: dts: uniphier: change phy-mode to 'internal' for LD11Kunihiko Hayashi
Change the phy-mode property to 'internal' that means to use a built-in PHY implemented on LD11 SoC. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-05-23ARM: dts: uniphier: add clock-names and reset-names to ethernet nodeKunihiko Hayashi
Add clock-names and reset-names because this node recognizes multiple clocks and resets. ("ether", and so on, for each) Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-05-23ARM: dts: uniphier: add required clocks and resets to Pro4 ethernet nodeKunihiko Hayashi
The GIO clock/reset, another MAC clock, and the PHY clock are required for the ethernet of Pro4 SoC. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-05-23ARM: dts: uniphier: add syscon-phy-mode property to each ethernet nodeKunihiko Hayashi
Add syscon-phy-mode property specifying a phandle of system controller to each ethernet node. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-05-20SPDX: Fixup SPDX tags in a few new filesTom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-20Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
2018-05-20Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini
2018-05-20Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini
2018-05-20ARM: rmobile: Unify Gen2 Makefile entryMarek Vasut
Drop per-SoC Makefile entries and replace them with one unified entry now that the PFC tables are gone. Shuffle the Makefile around a bit to make it more organized. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-05-20ARM: rmobile: Drop old R8A7794 PFC tablesMarek Vasut
All the boards use new modern PFC framework, the old PFC tables are no longer used, so remove them. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-05-20ARM: rmobile: Drop old R8A7793 PFC tablesMarek Vasut
All the boards use new modern PFC framework, the old PFC tables are no longer used, so remove them. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-05-20ARM: rmobile: Drop old R8A7792 PFC tablesMarek Vasut
All the boards use new modern PFC framework, the old PFC tables are no longer used, so remove them. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-05-20ARM: rmobile: Drop old R8A7791 PFC tablesMarek Vasut
All the boards use new modern PFC framework, the old PFC tables are no longer used, so remove them. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-05-20ARM: rmobile: Drop old R8A7790 PFC tablesMarek Vasut
All the boards use new modern PFC framework, the old PFC tables are no longer used, so remove them. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-05-20ARM: rmobile: Update V2H BlancheMarek Vasut
The V2H Blanche port was broken since some time. This patch updates the V2H Blanche port to use modern frameworks, DM, DT probing, SPL for the preloading and puts it on par with the M2 Porter board. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-05-18Fixup various SPDX tags from the latest mergeTom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-18arm64: zynqmp: Use DWC3 generic driver and DM_USBMichal Simek
Remove harcoded XHCI lists and detect mode, speed based on DT. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Serial-changes: 2 - Remove also XHCI macros from hardware.h - Remove additional new line in zcu106
2018-05-18Merge git://git.denx.de/u-boot-imxTom Rini
2018-05-18arm: dts: socfpga: stratix10: update dtsi and dtsLey Foon Tan
Update dtsi and dts files for resets, phy node and other properties. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-05-18arm: socfpga: misc: Add CONFIG_SYS_L2_PL310 switchLey Foon Tan
Preparation for Stratix 10 enablement. In ARM64, L2 cache controller is accessed through processor registers. So, add CONFIG_SYS_L2_PL310 switch conditional build in order this file can by shared across other SOCFPGAs. Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-05-18arm: socfpga: stratix10: Add pinmux support for Stratix10 SoCLey Foon Tan
Add pinmux driver support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-05-18arm: socfpga: stratix10: Add reset manager driver for Stratix10 SoCLey Foon Tan
Add Reset Manager driver support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-05-18arm: socfpga: stratix10: Add clock manager driver for Stratix10 SoCLey Foon Tan
Add Clock Manager driver support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-05-18arm: socfpga: stratix10: Add watchdog and firewall base addressesLey Foon Tan
Add the base address for watchdog and firewall. Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-05-18ARM: socfpga: Fix Documentation errors in scu_registersBen Kalo
According to ARM Cortex-A9 MPCore TRM section 2.2 - SCU registers Access Control register offset is 0x50. Signed-off-by: Ben Kalo <ben.h.kalo@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
2018-05-18ARM: socfpga: Adding SoCFPGA info for both SPL and U-BootTien Fong Chee
SoC FPGA info is required in both SPL and U-Boot. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2018-05-18ARM: socfpga: Adding clock frequency info for U-BootTien Fong Chee
Clock frequency info is required in U-Boot because info would be erased when transition from SPL to U-Boot. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2018-05-18configs: Add DDR Kconfig support for Arria 10Tien Fong Chee
This patch enables DDR Kconfig support for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18ARM: socfpga: Add DDR driver for Arria 10Tien Fong Chee
Add DDR driver support for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2018-05-18ARM: socfpga: Add DRAM bank size initialization functionTien Fong Chee
Add function for both multiple DRAM bank and single DRAM bank size initialization. This common functionality could be used by every single SOCFPGA board. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Tested-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-05-18ARM: socfpga: Rename the gen5 sdram driver to more specific nameTien Fong Chee
Current sdram driver is only applied to gen5 device, hence it is better to rename sdram driver to more specific name which is related to gen5 device. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2018-05-18ARM: socfpga: Repair A10 EMAC reset handlingMarek Vasut
The EMAC reset and PHY mode configuration was never working on the Arria10 SoC, fix this. This patch pulls out the common code into misc.c and passes the SoC-specific function call in as a function pointer. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18ARM: socfpga: Synchronize Arria10 SoCDK SDMMC handoffMarek Vasut
Regenerate Altera Arria 10 SoCDK SDMMC handoff file using latest Quartus to get the new set of clock bindings in. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18ARM: socfpga: Synchronize Arria10 DTsMarek Vasut
Synchronize Altera Arria 10 DT sources with Linux 4.16.3 as of commit ef8216d28a5920022cddcb694d2d75bd1f0035ca Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18ARM: socfpga: Sort the DT MakefileMarek Vasut
Sort the Makefile entries, no functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18ARM: socfpga: Sync A10 clock manager binding parserMarek Vasut
The A10 clock manager parsed DT bindings generated by Quartus the bsp-editor to configure the A10 clocks. Sadly, those DT bindings changed at some point. The clock manager patch used the old ones, this patch replaces the bindings parser with one for the new set. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18ARM: socfpga: Convert to DM serialMarek Vasut
Pull the serial port configuration from DT and use DM serial instead of having the serial configuration in two places, DT and board config. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18ARM: socfpga: Clean up Kconfig entriesMarek Vasut
Shuffle the default Kconfig entries around so it is not such a mess. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18ARM: socfpga: Zap CONFIG_SOCFPGA_VIRTUAL_TARGETMarek Vasut
This was never used, is not used anywhere and is just in the way by adding annoying ifdeffery. Get rid of it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18arm: imx53: Add support for imx53 boards from K+PLukasz Majewski
This commit adds support for DDC and HSC boards from K+P in u-boot. Console output: U-Boot 2018.05-rc2-00090-g752b7ed6f9 (Apr 26 2018 - 14:24:24 +0200) CPU: Freescale i.MX53 rev2.1 at 800 MHz Reset cause: WDOG Model: K+P iMX53 DRAM: 512 MiB MMC: FSL_SDHC: 0 Loading Environment from MMC... OK In: serial Out: serial Err: serial Module EEPROM: ID: TQMa53-CB.0401 SN: 63152762 MAC: 00:0b:64:03:14:2a BBoard:40x0 Rev:10 Net: eth0: ethernet@63fec000 Hit any key to stop autoboot: 0 Signed-off-by: Lukasz Majewski <lukma@denx.de>
generated by cgit (git 2.34.1) at 2024-12-30 20:53:06 +0000