| Age | Commit message (Collapse) | Author |
|---|
|
|
|
This patch undoes the patch by Jeff Mann with commit-id ada4697d. As
suggested by AMCC it is not recommended to dynamically change the EBC
speed after bootup. So we undo this change to be on the safe side.
Signed-off-by: Stefan Roese <sr@denx.de>
|
|
Signed-off-by: Stefan Roese <sr@denx.de>
|
|
Because the Sequoia board does not boot with an EBC faster than 66MHz,
the clock divider are changed after the initial boot process.
This allows for maximum clocking speeds to be achieved on newer boards.
Sequoia boards with 666.66 MHz processors require that the EBC divider
be set to 3 in order to start the initial boot process at a slower EBC
speed. After the initial boot process, the divider can be set back to 2,
which will cause the boards to run at 83.333MHz. This is backward
compatible with boards with 533.33 MHz processors, as these boards will
already be set with an EBC divider of 2.
Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com>
|
|
Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
for the 4k NAND boot image so define bus_frequency to 133MHz here
which is save for the refresh counter setup.
Signed-off-by: Stefan Roese <sr@denx.de>
|
|
|
|
Signed-off-by: Stefan Roese <sr@denx.de>
|
|
Signed-off-by: Stefan Roese <sr@denx.de>
|
|
Signed-off-by: John Otken john@softadvances.com <john@softadvances.com>
|
|
As provided by the AMCC applications team, this patch optimizes the
DDR2 setup for 166MHz bus speed. The values provided are also save
to use on a "normal" 133MHz PLB bus system. Only the refresh counter
setup has to be adjusted as done in this patch.
For this the NAND booting version had to include the "speed.c" file
from the cpu/ppc4xx directory. With this addition the NAND SPL image
will just fit into the 4kbytes of program space. gcc version 4.x as
provided with ELDK 4.x is needed to generate this optimized code.
Signed-off-by: Stefan Roese <sr@denx.de>
|
|
Some code cleanup.
|
|
Now the board revision and the current PCI bus speed are printed after
the board message.
Signed-off-by: Stefan Roese <sr@denx.de>
|
|
This fix will make the MAL burst disabling patch for the Linux
EMAC driver obsolete.
Signed-off-by: Stefan Roese <sr@denx.de>
|
|
This code will optimize the DDR2 controller setup on a board specific
basis.
Note: This code doesn't work right now on the NAND booting image for the
Sequoia board, since it doesn't fit into the 4kBytes for the SPL image.
Signed-off-by: Stefan Roese <sr@denx.de>
|
|
Now 32MByte and 64MByte FLASH is know to work and other
configurations should work too.
Signed-off-by: Stefan Roese <sr@denx.de>
|
|
|
|
Based on patch by Mike Frysinger, 20 Jun 2006
|
|
|
|
Patch by Stefan Roese, 23 Sep 2006
|
|
Patch by Stefan Roese, 13 Sep 2006
|
|
Patch by Stefan Roese, 12 Sep 2006
|
|
- Add support for PPC440EPx & PPC440GRx
- Add support for PPC440EP(x)/GR(x) NAND controller
in cpu/ppc4xx directory
- Add NAND boot functionality for Sequoia board,
please see doc/README.nand-boot-ppc440 for details
- This Sequoia NAND image doesn't support environment
in NAND for now. This will be added in a short while.
Patch by Stefan Roese, 07 Sep 2006
|
