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Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Drop changes for PEP 4 following python tools]
Signed-off-by: Tom Rini <trini@ti.com>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini Don't remove some copyrights by accident]
Signed-off-by: Tom Rini <trini@ti.com>
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Now that we assume dtc supports the -i option, we don't need to use
ARCH_CPU_DTS in *.dts{,i}; we simply specify the include filename
directly, and dtc will find it.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
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Add a memory-mapped 8GB SPI chip.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This is currently set to coreboot.dtsi, but we cannot support this on
old device tree compilers (dtc <= 1.3), so adjust to use ARCH_CPU_DTS
to let the Makefile preprocessor sort this out.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This contains just the minimum information for a coreboot-based board.
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
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The device tree now includes the necessary console configuration
information.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
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This file is no longer needed for coreboot.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Now that coreboot doesn't need the start16 code, remove it. We need
to remove the CONFIG_SYS_X86_RESET_VECTOR option from coreboot.h also.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This prevents the preprocessor from complaining when processing
variadic macros
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
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coreboot.c and coreboot_pci.c don't contain board specific but only
coreboot specific code. Hence move it to the coreboot directory in
arch/x86/cpu (which should probably be moved out of cpu/ in another
commit)
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
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This change also forces the lib_sysinfo structure to be in the .data
section. Otherwise it ends up in the .bss section. U-boot assumes that it
doesn't need to copy it over during relocation, and instead fills that
whole section with zeroes. If we really were booting from ROM that would be
appropriate, but we need some information from the coreboot tables (memory
size) before then and have to fill that structure before relocation. We
skirt u-boot's assumption by putting this in .data where it assumes there
is still read only but non-zero data.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
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Add a target for running u-boot as a coreboot payload in boards.cfg, a
board, CPU and a config. This is a skeleton implementation which always
reports the size of memory as 64 MB.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
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