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2018-12-10Merge tag 'fsl-qoriq-for-v2019.01-rc2' of git://git.denx.de/u-boot-fsl-qoriqTom Rini
Add TFA boot flow for some Layerscape platforms Add support for lx2160a SoC [trini: Add a bunch of missing MAINTAINERS entries] Signed-off-by: Tom Rini <trini@konsulko.com>
2018-12-06armv8: ls1046ardb: Add TFABOOT supportRajesh Bhagat
TFABOOT support includes: - ls1046ardb_tfa_defconfig to be loaded by trusted firmware - environment address and size changes for TFABOOT - FMAN address changes for TFABOOT - define BOOTCOMMAND for TFABOOT Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
2018-08-10armv8: ls1046a: initial icid setup supportLaurentiu Tudor
Add infrastructure for ICID setup and device tree fixup on ARM platforms. This include basic ICID setup for several devices. Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-07-31ls1046ardb: Add qspi_spl variant to the MAINTAINERS fileTom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-07-26armv8: ls1046ardb: Add falcon mode for for QSPI bootYork Sun
A new defconfig is introduced to support SPL boot from QSPI NOR flash. This is to support falcon mode for faster booting into Linux. Signed-off-by: York Sun <york.sun@nxp.com>
2018-06-08board: Kconfig: Re-Arrangement of PPA firmware and header addressesBhaskar Upadhaya
PPA firmware and header address may vary depending upon different boards, configure ppa firmware and header address in board specific Kconfig. Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com> Signed-off-by: Jagdish Gediya <jagdish.gediya@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-01-30armv8: ls1046ardb: Add RDIMM supportYork Sun
This adds 2Rx8 RDIMM on LS1046ARDB board. Tested with RDIMM MTA18ASF2G72PDZ and MTA9ASF1G72PZ. Signed-off-by: York Sun <york.sun@nxp.com>
2017-12-24boards: ls1046ardb: disable unavailable "ethernet" node in dtsPrabhakar Kushwaha
Linux device tree contains "ethernet" node for all possible interface supported by SoC i.e. LS1046A. It is not necessary for a SerDes protocol to support all possible interface. So disable unavailable "ethernet" node in device tree. Also, enable FDT_SEQ_MACADDR_FROM_ENV to fetch MAC address sequentially from environment variables Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-09fsl-lsch2: csu: remove multiple calling functionHou Zhiqiang
Function enable_layerscape_ns_access() is alreayd called soc-wide. Remove duplicated calling from individual boards. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [YS: Add commit message] Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-09armv8: ls1046ardb: update core frequency to 1800MHZQianyu Gong
Update the default core frequency to 1800MHZ for best performance under SD boot and eMMC boot. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-06-05common: freescale: Move arch-specific declarationsSimon Glass
The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-05-23armv8: layerscape: Adjust memory mapping for Flash/SD card on LS1046AAlison Wang
This patch is to adjust the memory mapping for FLash/SD card on LS1046AQDS and LS1046ARDB, such as FMAN firmware load address, U-Boot start address on serial flash and environment address. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-05-23armv8: ls1046ardb: Make NET independent of FManYork Sun
This allows using PCIe NIC without enabling DPAA FMan. Signed-off-by: York Sun <york.sun@nxp.com> CC: Mingkai Hu <mingkai.hu@nxp.com> Acked-by: Mingkai Hu <mingkai.hu@nxp.com>
2017-04-24armv8: layerscape: Fix DDR size calcuation for SPL buildYork Sun
Commit 088454cd dropped return value from initram(), setting gd->ram_size directly. Three boards were missed for SPL boot. Signed-off-by: York Sun <york.sun@nxp.com>
2017-04-17arm: ls1046ardb: Add SD secure boot targetRuchika Gupta
- Add SD secure boot target for ls1046ardb. - Change the u-boot size defined by a macro for copying the main U-Boot by SPL to also include the u-boot Secure Boot header size as header is appended to u-boot image. So header will also be copied from SD to DDR. - CONFIG_MAX_SPL_SIZE is limited to 90KB. SPL is copied to OCRAM (128K) where 32K are reserved for use by boot ROM and 6K for the header. - Reduce the size of CAAM driver for SPL Blobification functions and descriptors, that are not required at the time of SPL are disabled. Further error code conversion to strings is disabled for SPL build. Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17armv8: LS1046ARDB: Add QSPI Secure Boot targetVinitha Pillai-B57223
Add QSPI Secure Boot target. Also enable sec init. Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17armv8: ls1046ardb: SPL size reductionSumit Garg
Using changes in this patch we were able to reduce approx 4k size of u-boot-spl.bin image. Following is breif description of changes to reduce SPL size: 1. Changes in board/freescale/ls1046ardb/Makefile to remove compilation of eth.c and cpld.c in case of SPL build. 2. Changes in board/freescale/ls1046ardb/ls1046ardb.c to keep only ddr_init and board_early_init_f funcations in case of SPL build. 3. Changes in ls1046a_common.h & ls1046ardb.h to remove driver specific macros due to which static data was being compiled in case of SPL build. 4. Disable MMC driver from bieng compiled in case of SPL NAND build and NAND driver from bieng compiled in case of SPL MMC build. Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-12arm: freescale: Rename initdram() to fsl_initdram()Simon Glass
This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-04-05board_f: Drop return value from initdram()Simon Glass
At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2017-04-05board_f: Drop board_type parameter from initdram()Simon Glass
It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2017-03-14armv8: layerscape: Update early MMU for DDR after initializationYork Sun
In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-14armv8: layerscape: Rewrite memory reservationYork Sun
For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-18ls1046ardb: Add support power initializationHou Zhiqiang
Add the chip power supply voltage initialization on LS1046ARDB. Add function power_init_board(), and it will initialize the PMIC and call the chip power initialization function. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18ls1046ardb: cpld: add API for selecting core voltHou Zhiqiang
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-12-15fsl/board/ddr: optimize board-specific cpo for erratum A-009942Shengzhou Liu
Optimize board-specific cpo for erratum A-009942 on b4860qds, ls1043aqds, ls1043ardb, ls1046aqds, ls1046ardb, ls2080ardb, t102xqds, t102xrdb, t1040qds, t104xrdb, t208xqds, t208xrdb, t4qds, t4rdb boards. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-09-14armv8: ls1046ardb: Add LS1046ARDB board supportMingkai Hu
LS1046ARDB Specification: ------------------------- Memory subsystem: * 8GByte DDR4 SDRAM (64bit bus) * 512 Mbyte NAND flash * Two 64 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card * On-board 4G eMMC Ethernet: * Two XFI 10G ports * Two SGMII ports * Two RGMII ports PCIe: * PCIe1 (SerDes2 Lane0) to miniPCIe slot * PCIe2 (SerDes2 Lane1) to x2 PCIe slot * PCIe3 (SerDes2 Lane2) to x4 PCIe slot SATA: * SerDes2 Lane3 to SATA port USB 3.0: one super speed USB 3.0 type A port one Micro-AB port UART: supports two UARTs up to 115200 bps for console Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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