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2009-06-0985xx: Fix the clock adjust of mpc8569mds boardDave Liu
Currently the clk_adj is 6 (3/4 cycle), The settings will cause the DDR controller hang at the data init. Change the clk_adj from 6 to 4 (1/2 cycle), make the memory system stable. Signed-off-by: Dave Liu <daveliu@freescale.com>
2009-04-04fsl_pci: Move prototypes into fsl_pci.h and remove explicit externsKumar Gala
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-04-04fsl_pci: Renamed immap_fsl_pci.h to fsl_pci.hKumar Gala
Rename the pci header for FSL HW so we can move some prototypes in there and stop doing explicit externs Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-03-30MPC85xx: Add MPC8569MDS board supportHaiying Wang
This patch adds MPC8569MDS board support. The UART, QE UEC1 and UEC2, BRD EEPROM on I2C2 bus, PCI express and DDR3 SPD are supported in this patch. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Hillel Avni <Hillel.Avni@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>