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2013-07-24Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
2011-04-04powerpc/85xx: Add 36-bit physical addressing support for P1_P2_RDBPoonam Aggrwal
Add support for 36-bit address map for NOR, SD, and SPI boot cfgs. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <priyanka.jain@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04powerpc/85xx: Use DDR for RAMBOOT instead of L2 SRAM on p1_p2_rdbPriyanka Jain
Using DDR as RAMBOOT base instead of L2SRAM for SDCard and SPI Flash boot loaders because: - P1_P2_RDB boards have soldered DDR so no need for SPD - Also P102x has 256K L2 cache size so becomes a limiting factor for size of image that could be loaded in SRAM mode and would require three stage boot loader (TPL). Changes done: 1. CONFIG_SYS_TEXT_BASE to 0x11000000 2. CONFIG_RESET_VECTOR_ADDRESS to 0x1107fffc Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com> Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-03-24powerpc/85xx: Fix PCI memory map setup on P1_P2_RDBPrabhakar Kushwaha
Update the PCIe address map to match standard FSL memory map. Additionally, fix the TLBs so the cover the PCIe address space properly so cards plugged in like an e1000 work correctly. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19ppc/85xx: Fix compile err when PCI disabled on P1_P2_RDBPrabhakar Kushwaha
u-boot cannot be compiled after disabling CONFIG_PCI. Place PCI related codes under #ifdef CONFIG_PCI Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05ppc/85xx: Map boot page guarded for MP bootKumar Gala
We already map the page cache-inhibited. There is no reason we shouldn't also be marking it guarded to prevent speculative accesses. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-16ppc/P1_P2_RDB: NAND Boot SupportDipen Dudhat
NAND Boot support for P1 and P2 series RDB platforms. This patch is derived from NAND Boot support on MPC8536DS. Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-2885xx: Add support for P2020RDB boardPoonam Aggrwal
The code base adds P1 & P2 RDB platforms support. The folder and file names can cater to future SOCs of P1/P2 family. P1 & P2 processors are 85xx platforms, part of Freescale QorIQ series. Tested following on P2020RDB: 1. eTSECs 2. DDR, NAND, NOR, I2C. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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