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Some board ports place TEXT_BASE at a location that would cause the
RESET_VECTOR_ADDRESS not to be at 0xfffffffc when we link. By default
we assume RESET_VECTOR_ADDRESS will be 0xfffffffc if the board doesn't
explicitly set it.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>
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Refactor the code into a simple bitmask lookup table that determines if
a given PCI controller is enabled and if its in host/root-complex or
agent/end-point mode.
Each processor in the PQ3/MPC86xx family specified different encodings
for the cfg_host_agt[] and cfg_IO_ports[] boot strapping signals.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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There are really no differences between all the 85xx linker scripts so
we can just move to a single common one. Board code is still able to
override the common one if need be.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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For historic reasons we had defined some additional PLATFORM_CPPFLAGS
like:
PLATFORM_CPPFLAGS += -DCONFIG_E500=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1
However these are all captured in the config.h and thus redudant.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Every platform that calls fsl_pci_init calls fsl_pci_setup_inbound_windows
before it calls fsl_pci_init. There isn't any reason to just call it
from fsl_pci_init and simplify things a bit.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Every platform that calls fsl_pci_init calls pci_setup_indirect before
it calls fsl_pci_init. There isn't any reason to just call it from
fsl_pci_init and simplify things a bit.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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The pixis code used in8/out8 all over the place. Replace it with
in_8/out_8 macros.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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The p2020DS, MPC8536DS, MPC8572DS, MPC8544DS boards are capable of
swizzling the upper address bits of the NOR flash we boot out of which
creates the concept of "virtual" banks. This is useful in that we can
flash a test of image of u-boot and reset to one of the virtual banks
while still maintaining a working image in "bank 0".
The PIXIS FPGA exposes registers on LBC which we can use to determine
which "bank" we are booting out of (as well as setting which bank to
boot out of).
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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The patch adds support for P2020DS reference platform.
DDR3 interface uses hard-coded initialization rather than SPD
for now and was tested at 667Mhz. Some PIXIS register
definitions and associated code sections need to be fixed.
TSEC1/2/3, NOR flash, MAC/SYS ID EEPROM, PCIE1/2/3 are all
tested under u-boot.
Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Travis Wheatley <Travis.Wheatley@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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