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2019-08-11env: Drop environment.h header file where not neededSimon Glass
This header file is now only used by files that access internal environment features. Drop it from various places where it is not needed. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-11env: Move env_get() to env.hSimon Glass
Move env_get() over to the new header file. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-11env: Move env_set() to env.hSimon Glass
Move env_set() over to the new header file. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-11env: Move env_set_hex() to env.hSimon Glass
Move env_set_hex() over to the new header file along with env_set_addr() which uses it. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-08-11env: Move env_init() to env.hSimon Glass
Move env_init() over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-08-11env: Move env_get_f() to env.hSimon Glass
Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-29video: fsl_dcu_fb: refactor init functionsIgor Opaniuk
Move dcu-related code to fsl_dcu_probe_common, keep in video_hw_init() only legacy video stack (filling GraphicPanel struct etc.). Add wrappers for all init functions, that will let to provide struct fb_info as an additional param (needed for further moving it from the global scope to driver private data struct in DM converted driver). Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2019-07-27Merge tag 'u-boot-imx-20190719' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20190719 - CCF for i.MX6 - nandbcb command to write SPL into NAND - Switch to DM (i.MX28) - Boards: Toradex, engicam, DH - Fixes for i.MX8 - Fixes for i.MX7ULP Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/561147504
2019-07-25Add support for the NXP LS1021A-TSN boardJianchao Wang
The LS1021A-TSN is a development board built by VVDN/Argonboards in partnership with NXP. It features the LS1021A SoC and the first-generation SJA1105T Ethernet switch for prototyping implementations of a subset of IEEE 802.1 TSN standards. Supported boot media: microSD card (via SPL), QSPI flash. Rev. A of the board uses a Spansion S25FL512S_256K serial flash, which is 64 MB in size and has an erase sector size of 256KB (therefore, flashing the RCW would erase part of U-Boot). Rev. B and C of the board use a Spansion S25FL256S1 serial flash, which is only 32 MB in size but has an erase sector size of 64KB (therefore the RCW image can be flashed without erasing U-Boot). To avoid the problems above, the U-Boot base address has been selected at 0x100000 (the start of the 5th 256KB erase sector), which works for all board revisions. Actually 0x40000 would have been enough, but 0x100000 is common for all Layerscape devices. eTSEC3 is connecting directly to SJA1105 via an RGMII fixed-link, but SJA1105 is currently not supported by uboot. Therefore, eTSEC3 is disabled. Signed-off-by: Xiaoliang Yang <xiaoliang.yang_1@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Jianchao Wang <jianchao.wang@nxp.com> Signed-off-by: Changming Huang <jerry.huang@nxp.com> Signed-off-by: Vladimir Oltean <olteanv@gmail.com> [Vladimir] Code taken from https://github.com/openil/u-boot (which itself is mostly copied from ls1021a-iot) and adapted with the following changes: - Add a008850 errata workaround - Converted eTSEC, MMC to DM to avoid all build warnings - Plugged in distro boot feature, including support for extlinux.conf - Added defconfig for QSPI boot - Added the board/freescale/ls1021atsn/README.rst for initial setup - Increased CONFIG_SYS_MONITOR_LEN so that the SPL malloc pool does not get overwritten during copying of the u-boot.bin payload from MMC to DDR. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-25arm: ls1021atwr: Convert to use driver model TSEC driverBin Meng
Now that we have added driver model support to the TSEC driver, convert ls1021atwr board to use it. This depends on previous DM series for ls1021atwr: http://patchwork.ozlabs.org/patch/561855/ Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> [Vladimir] Made the following changes: - Added 'status = "disabled";' for all Ethernet ports in ls1021a.dtsi - Fixed the confusion between the SGMII/TBI PCS for enet0 and enet1 - a mistake ported over from Linux. Each SGMII PCS lies on the private MDIO bus of the interface (and the RGMII enet2 has no SGMII PCS). - Added CONFIG_DM_ETH to all ls1021atwr_* defconfigs - Completely removed non-DM_ETH support from ls1021atwr - Changed "compatible" string from "fsl,tsec-mdio" to "fsl,etsec2-mdio" and from "fsl,tsec" to "fsl,etsec2" to match Linux
2019-07-19mx6sxsabresd: imximage.cfg: Handle the CONFIG_SECURE_BOOT caseBreno Matheus Lima
Secure boot is not enabled in mx6sxsabresd imximage.cfg, add support for it. Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-07-19arm: imx8: don't duplicate build_info()Anatolij Gustschin
Move build_info() to common place. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Cc: Peng Fan <peng.fan@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19arm: imx8: factor out uart init codeAnatolij Gustschin
New imx8 boards started adding duplicated UART init code. Factor out this to common function sc_pm_setup_uart(). Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19mx7ulp_evk: Update DDR freq to 352.8Mhz for ULP B0Ye Li
On i.MX7ULP B0, the DDR clock target is increased from 320Mhz to 380Mhz. We update DDR clock relevant settings to approach the target. But since the limitation on LCDIF pix clock for HDMI output (refer "mx7ulp_evk: Change APLL and its PFD0 frequencies"), we set DDR clock to 352.8Mhz (25.2Mhz * 14) by using the clock path: APLL PFD0 -> DDR CLK -> NIC0 -> NIC1 -> LCDIF clock To reduce the impact to entire system, the NIC0_DIV and NIC1_DIV are kept, so the divider 14 is calculated as: 14 = (NIC0_DIV + 1) * (NIC1_DIV + 1) * (LCDIF_PCC_DIV + 1) NIC0_DIV: 1 NIC1_DIV: 0 LCDIF_PCC_DIV: 6 APLL and APLL PFD0 settings: PFD0 FRAC: 27 APLL MULT: 22 APLL NUM: 1 APLL DENOM: 20 This patch applies the new settings for both DCD and plugin. There is no DDR script change on this new frequency. Overnight memtester is passed. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19mx7ulp: Select the SCG1 APLL PFD as a system clock sourceYe Li
Due to the APLL out glitch issue, the APLLCFG PLLS bit must be set to select SCG1 APLL PFD for generating system clock to align with the design. Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com>
2019-07-19mx7ulp_evk: Change APLL and its PFD0 frequenciesYe Li
To support HDMI display on EVK board, the LCDIF pix clock must be 25.2Mhz. Since the its PCC divider range is from 1-8, the max rate of LCDIF PCC source clock is 201.6Mhz. This limits the source clock must from NIC1 bus clock or NIC1 clock, other sources from APLL PFDs are higher than this max rate. The NIC1 bus clock and NIC1 clock are from DDRCLK whose parent source is APLL PFD0, so we must change the APLL PFD0 and have impact to DDRCLK, NIC1 and NIC1 bus. Eventually, this requests to set the APLL PFD0 frequency to 302.4Mhz (25.2 * 12), with settings: PFD0 FRAC: 32 APLL MULT: 22 APLL NUM: 2 APLL DENOM: 5 Signed-off-by: Ye Li <ye.li@nxp.com> Tested-by: Fancy Fang <chen.fang@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-19mx7ulp_evk: Update LPDDR3 scriptYe Li
Update LPDDR3 script with the changes below: -Update the precharge command to CMD=01 at the DDR initialization phase -remove unimplemented registers Write data bit delay --refer to the DDR_TRIM bits in IOMUXC1_DDR_SW_PAD_CTL_PAD_DDRn Test: One EVK board passes overnight stress test. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-19mx7ulp: Fix APLL num and denom setting issueYe Li
For the current APLL setting, as we want the APLL PFD0 to meet DDR clock 320Mhz requirement. We set MULT to 20, NUM to 4 and DENOM to 2, to get final 22 multiplier. But according to the RM, the NUM should always be less than the DENOM. So our setting violates the rule. Actually the ROM has already set the MULT to 22 and leave NUM/DENOM in default value. The calculated APLL PFD0 clock is 318.9888Mhz, which also meet the DDR requirement. To fix the issue, we remove the PLL settings in DCD to use default value from ROM, and only set the PFD0 FRAC. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-06-23Convert to use fsl_esdhc_imx for i.MX platformsYangbo Lu
Converted to use fsl_esdhc_imx for i.MX platforms. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Tested-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Martyn Welch <martyn.welch@collabora.com> Acked-by: Jason Liu <Jason.hui.liu@nxp.com>
2019-06-20Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xxTom Rini
- PCIe driver change to support DM model - T2080QDS migrated to use PCIe DM model
2019-06-20powerpc: T208xQDS: Compile the legacy PCIe routines conditionallyHou Zhiqiang
Compile the legacy PCIe initialization reoutines only when DM_PCI is not enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19board/freescale/common: secure_boot: Set bootdelay to -2.Udit Agarwal
Uboot prompt must not be available while running secure boot. TO ensure this bootdelay must be set to -2. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: ls1046afrwy: Add support for LS1046AFRWY platformVabhav Sharma
LS1046AFRWY board supports LS1046A family SoCs. This patch add base support for this board. Board support's 4GB ddr memory, i2c, micro-click module,microSD card, serial console,qspi nor flash,ifc nand flash,qsgmii network interface, usb 3.0 and serdes interface to support two x1gen3 pcie interface. Signed-off-by: Camelia Groza <camelia.groza@nxp.com> Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: ls1028a: Add secure boot defconfigYuantian Tang
Add secure boot defconfig for ls1028aqds and ls1028ardb boards. Signed-off-by: Yuantian Tang <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19board: lx2160a: fix fsl-mc status in fdt with bootefiMian Yousaf Kaukab
fsl-mc lazyapply command applies dpl from efi_exit_boot_services(). Status of fsl-mc node in working fdt is updated at this stage. However, an efi application like grub may already have copied the fdt. So the updates to fdt done at efi_exit_boot_services() may not be visible to the OS. Fix it by updating fdt earlier if fsl-mc lazyapply command is used. Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19board/fsl/layerscape: Modify the aliases namesPankaj Bansal
when compiling dts file using DTC_FLAG='-@', the device tree compiler reports these warnings: Warning (alias_paths): /aliases: aliases property name must include only lowercase and '-' Fixed the node aliases to silence these warnings. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-11imx8mq_evk: Staticize when appropriateFabio Estevam
Staticize 'spl_dram_init' and 'i2c_pad_info1' to fix the following sparse warnings: board/freescale/imx8mq_evk/spl.c:30:6: warning: symbol 'spl_dram_init' was not declared. Should it be static? board/freescale/imx8mq_evk/spl.c:41:22: warning: symbol 'i2c_pad_info1' was not declared. Should it be static? Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-06-11mx6sabresd: Remove U-Boot proper mmc initializationFabio Estevam
After the conversion to DM there is no need to have mmc initialization code inside U-Boot proper. Remove the unneeded code. Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-05-22board: fsl: lx2160ardb: invert AQR107 pins polarityFlorin Chiculita
AQR107 PHYs interrupt pins are active-low, while the GIC expects a level-high signal. Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22armv8: ls1028aqds: Add support of LS1028AQDSYuantian Tang
LS1028AQDS Development System is a high-performance computing, evaluation, and development platform that supports LS1028A QorIQ Architecture processor. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang yuantian <andy.tang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22armv8: ls1028ardb: Add support for LS1028ARDBYuantian Tang
LS1028A is an ARMv8 implementation. LS1028ARDB is an evaluation platform that supports the LS1028A family SoCs. This patch add basic support of the platform. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-21mpc83xx: Get rid of CONFIG_SYS_LBC_*Mario Six
Except for one counter example, CONFIG_SYS_LBC_LBCR always has a value of either 0x00040000 or 0x00000000. CONFIG_SYS_LBC_MRTPR always has the value 0x20000000. CONFIG_SYS_LBC_LSDMR_{1,2,4,5} are not set for any mpc83xx board. CONFIG_SYS_LBC_LSRT is set by one board (to 0x32000000). To simplify the configuration files, hardcode the setting of these values for mpc83xx. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21mpc83xx: Get rid of CONFIG_SYS_DDR_SDRAM_BASEMario Six
CONFIG_SYS_DDR_SDRAM_BASE is set to the same value as CONFIG_SYS_SDRAM_BASE on all existing boards. Just use CONFIG_SYS_SDRAM_BASE instead. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21mpc83xx: Get rid of CONFIG_SYS_DDR_BASEMario Six
CONFIG_SYS_DDR_BASE is specific to mpc83xx an is always set to the same value as CONFIG_SYS_SDRAM_BASE. Just use CONFIG_SYS_SDRAM_BASE instead. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21mpc83xx: Migrate CONFIG_SYS_{BR, OR}*_PRELIM to KconfigMario Six
Migrate the BR/OR settings to Kconfig. These must be known at compile time, so cannot be configured via DT. Configuration of this crucial variable should still be somewhat comfortable. Hence, make its fields configurable in Kconfig, and assemble the final value from these. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21mpc83xx: Kconfig: Migrate HRCW to KconfigMario Six
The HRCW (hardware reset configuration word) is a constant that must be hard-coded into the boot loader image. So, it must be available at compile time, and cannot be migrated to the DT mechanism, but has to be kept in Kconfig. Configuration of this crucial variable should still be somewhat comfortable. Hence, make its fields configurable in Kconfig, and assemble the final value from these. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21mpc83xx: Get rid of CONFIG_83XX_CLKINMario Six
MPC83xx uses CONFIG_83XX_CLKIN instead of CONFIG_SYS_CLK_FREQ to set the system clock. To migrate the architecture, we can replace CONFIG_83XX_CLKIN with CONFIG_SYS_CLK_FREQ. To do this * replace all occurrences of CONFIG_83XX_CLKIN with CONFIG_SYS_CLK_FREQ * set CONFIG_SYS_CLK_FREQ to the old value of CONFIG_83XX_CLKIN in all MPC83xx config files Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21mpc83xx: Migrate legacy PCI options to KconfigMario Six
The MPC83xx include files contain some settings of the PCI subsystem. Migrate these to Kconfig until a proper DM PCI driver exists. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21MPC8349ITX: Migrate to CONFIG_TARGET_MPC8349ITXMario Six
Use the proper CONFIG_TARGET_MPC8349ITX Kconfig option to replace the CONFIG_MPC8349ITX ad-hoc config option. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21MPC832XEMDS: Migrate to CONFIG_TARGET_MPC832XEMDSMario Six
Use the proper CONFIG_TARGET_MPC832XEMDS Kconfig option to replace the CONFIG_MPC832XEMDS ad-hoc config option. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21mpc83xx: Make distinct MPC8349EMDS_SDRAM boardMario Six
The MPC8349EMDS config file contains config options to enable SDRAM support. To keep this ability after the Kconfig migration, create a new MPC8349EMDS_SDRAM board that enables the SDRAM support and remove the SDRAM support from the original board. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-20mpc83xx: Make distinct MPC8313ERDB targetsMario Six
MPC8313ERDB has the option of either enabling NOR or NAND boot in its config file (by commenting out certain #ifdefs). To keep this ability after migrating options to Kconfig, we introduce two MPC8313ERDB configs: one for NOR, and one for NAND. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-04-25imx8qxp_mek: drop warning due to unused variableStefano Babic
Signed-off-by: Stefano Babic <sbabic@denx.de>
2019-04-25imx: support i.MX8QM MEK boardPeng Fan
Add i.MX8QM MEK board support. Included a basic dts, enabled SPL FIT Boot log as below: U-Boot SPL 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30 +0800) Normal Boot Trying to boot from MMC2_2 U-Boot 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30 +0800) CPU: NXP i.MX8QM RevB A53 at 142933 MHz Model: Freescale i.MX8QM MEK Board: iMX8QM MEK Build: SCFW 9330215b Boot: SD1 DRAM: 6 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... *** Warning - bad CRC, using default environment In: serial@5a060000 Out: serial@5a060000 Err: serial@5a060000 Net: Error: ethernet@5b040000 address not set. eth-1: ethernet@5b040000 Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-25imx8qxp: mek: enable dm-spl for pmPeng Fan
with u-boot,dm-spl added for imx8qx-pm node, and SPL_SIMPLE_BUS enabled, the bind and probe code in board file could be removed. Also we need to enlarge SYS_MALLOC_F_LEN to avoid calloc fail. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-13Add missing space in commentMarcel Ziswiler
Spotted two missing spaces in comments. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2019-04-02imx8mq_evk: README: Make the underline marker fill the whole sentenceFabio Estevam
Let the underline marker "=" fill the whole sentence for better readability. Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-04-02imx8mq_evk: README: Fix a typo in the destination pathFabio Estevam
The DDR firmware binaries should be copied to '$(srctree)', so fix a typo. Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-04-02imx8mq_evk: README: Need to copy bl31.bin to U-Boot source treeFabio Estevam
After building ATF it is needed to copy the generated bl31.bin file to the U-Boot source tree. Make this step explicit in the instructions. Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-03-15armv7: ls102xa: Add workaround for DDR erratum A-008850Alison Wang
Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workaround to fix the erratum. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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