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2013-05-24powerpc/t4240qds: Add VDD overrideYork Sun
Allow VDD voltage overriding with a command. This is an add-on feasture of VID. To override VDD, use command vdd_override with the value of voltage in mV, for example vdd_override <voltage in mV, eg. 1050> The above example will set the VDD to 1.050 volt. Any wrong value out of range of 0.8188 to 1.2125 volt or invalid string is ignored. In addition to the command, if overriding VDD is needed earlier in booting process, save an variable and reboot: setenv t4240qds_vdd_mv <voltage in mV> saveenv Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24powerpc/t4240qds: Add board detail for bdinfo commandYork Sun
Print more detail information including core voltage, RCW source, switch settings, etc. with bdinfo command. Signed-off-by: York Sun <yorksun@freescale.com> CC: Wolfgang Denk <wd@denx.de> CC: Tom Rini <trini@ti.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-16mx23evk: Add splash screen supportFabio Estevam
Enable display support. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-05-16mx28evk: Add splash screen supportFabio Estevam
Enable display support. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-05-14T4240/eth: fix SGMII card PHY addressShaohui Xie
QSGMII card assumed to be used by default, but if SGMII card is used, it will use different PHY address, but we don't know which card is used until we access PHY on the card. So we check the card type slot by slot, if we can read a PHY ID by reading a SGMII PHY address on a slot, then the slot must have a SGMII card pluged, we mark all ports on that slot, and fix dts to use the SGMII card PHY address when doing dts fixup for the marked ports. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14powerpc/t4qds: Fix disabling remote I2C connectionEd Swarthout
Only clear IRE bit in qixis brdcfg5 register and keep other bits unchanged. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14powerpc/b4860qds: Assign DDR address in board fileYork Sun
B4860QDS requires DDRC2 has 0 as base address and DDRC1 has higher address. This is the requirement for DSP cores to run in 32-bit address space. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14T4240/net: use QSGMII card PHY address by defaultShaohui Xie
Use QSGMII card PHY address as default SGMII card PHY address, QSGMII card PHY address is variable depends on different slot. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14t4240qds/eth: fixup ethernet for t4240qdsShengzhou Liu
1, Implemented board_ft_fman_fixup_port() to fix port for kernel. 2, Implemented fdt_fixup_board_enet() to fix node status of different slots and interfaces. 3, Adding detection of slot present for XGMII interface. 4, There is no PHY for XFI, so removed related phy address settings. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14powerpc/t4240qds: Add voltage ID supportYork Sun
T4240 has voltage ID fuse. Read the fuse and configure the voltage correctly. Core voltage has higher tolerance on over side than below. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14powerpc/t4240qds: Update DDR timing tableYork Sun
Update the timing table to support more rank density, based on the theory that similar density DIMMs have similar clock adjust and write level start timing. Update the timing for 1600 and 1866 MT/s. Tested with Micron MT18JSF1G72AZ-1G9E1 DIMMs, iDIMM M3CN-4GMJ3C0C-M92. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14T4/serdes: fix the serdes clock frequencyRoy Zang
Reverse the bit sequence to set and display serdes clock frequency correctly. The correct bit maps in BRDCFG2 are 0 1 2 3 4 5 6 7 S1RATE[1:0] S2RATE[1:0] S3RATE[1:0] S4RATE[1:0] Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-11Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD
Conflicts: drivers/mtd/nand/mxc_nand_spl.c include/configs/m28evk.h
2013-05-10Fix references to the documentation filesAnatolij Gustschin
Many boot image configuration files refer to the appropriate documentation file, but these references contain typos in the directory and file name. Fix them. Also fix reference to doc/README.SPL file. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
2013-05-06imx: mx35pdk: Fix MUX2_CTR GPIOBenoît Thébaudeau
MUX2_CTR is on GPIO1[5], not GPIO2[5], and it needs to be set high in order to connect the FEC. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-05-06mx23evk: Do not set voltage selection bit for SSP padsFabio Estevam
mx23 SSP pad registers do not contain voltage selection bit, so just remove it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-05-05imx: mx53smd: Convert to iomux-v3Benoît Thébaudeau
There is no change of behavior. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-05-05imx: mx53loco: Convert to iomux-v3Benoît Thébaudeau
There is no change of behavior. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-05-05imx: mx53evk: Convert to iomux-v3Benoît Thébaudeau
There is no change of behavior. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-05-05imx: mx53ard: Convert to iomux-v3Benoît Thébaudeau
There is no change of behavior. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-05-05imx: mx51evk: Convert to iomux-v3Benoît Thébaudeau
There is no change of behavior, except for older silicon revisions for which support is removed. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-05-05imx: mx35pdk: Convert to iomux-v3Benoît Thébaudeau
There is no change of behavior. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-05-05imx: mx35pdk: Fix WDOG_RST iomux functionBenoît Thébaudeau
The signal connected from this pin to the PMIC is WDOG_B, i.e. ALT0 mode, not ALT1 (which even corresponds to nothing). Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-05-05imx: mx25pdk: Fix GPIO assignmentsBenoît Thébaudeau
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-05-05imx: mx25pdk: Convert to iomux-v3Benoît Thébaudeau
There is no change of behavior, even if some pad control values could probably be simplified. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-05-05mx23evk: Fix DDR pin iomux settingsFabio Estevam
Change MUX_CONFIG_EMI to use the same drive strength as the bootlets code from Freescale, which results in much better stability. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-05-02powerpc/p1_p2_rdb_pc: Add a pin to reset the DDR chip for P1021RDB-PCXu Jiucheng
When P1021RDB-PC reboot system, the board will hung at uboot DDR configuration. For P1021RDB-PC DDR reset pin is multiplex with QE, so uboot will reserve this pin for QE and skip DDR reset. Other platforms without QE will do this reset. This patch adds a slight code to reset DDR chip by QE CE_PB8 pin for NAND and NOR FLASH boot. For booting from SPI FALSH and SD card, it seems possible to use the rom on chip to write to the GPIO pins before configuring the DDR. Signed-off-by: Xu Jiucheng <B37781@freescale.com> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02powerpc/p1010rdb: Change flexcan compatible stringShengzhou Liu
Change flexcan compatible string from "fsl,flexcan-v1.0" to "fsl,p1010-flexcan" to match the device tree. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02qoriq/p1_p2_rdb_pc: USB device-tree fixups for P1020Zhicheng Fan
Resolve P1020 second USB controller multiplexing with eLBC - mandatory to mention USB2 in hwconfig string to select it over eLBC, otherwise USB2 node is removed - works only for SPI and SD boot Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Zhicheng Fan <B32736@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02powerpc/b4860qds: Add the tlb entries for SRIO interfacesLiu Gang
Add the tlb entries based on the configuration of the SRIO interfaces. Every SRIO interface has 256M space: #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02powerpc/p1022ds: Add support for NAND and NAND boot using SPLMatthew McClintock
Add defines needed to access NAND, remove second flash bank that is actually connected to NAND. Add nand booting support for P1022DS with hardcoded DDR config using SPL framework from 2011 Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02board/freescale/common/cds_pci_ft.c: Fix rotate wrong cells in interrupt-map ↵Jiang Bin
property For linux 3.x, the size of each item in interrupt-map property is 9 not 7. Don't use the static value and calculate the size with following cells: PCI #address-cells, PCI #interrupt-cells, PIC address, PIC #address-cells, PIC #interrupt-cells. Signed-off-by: Bin Jiang <bin.jiang@windriver.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-01env_mmc: add support for redundant environmentMichael Heimpold
This patch add support for storing the environment redundant on mmc devices. Substantially it re-uses the logic from the NAND implementation, that means using an incremental counter for marking newer data. Signed-off-by: Michael Heimpold <mhei@heimpold.de>
2013-04-28imx: iomux-v3: Include PKE and PUE to pad control pull definitionsBenoît Thébaudeau
PUE requires PKE to mean something, as do pull values with PUE, so do not compell users to explicitly use PKE and PUE everywhere. This is also what is done on Linux and what has already been done for i.MX51. By the way, remove some unused pad control definitions. There is no change of behavior. Note that SPI_PAD_CTRL was defined by several boards with a pull value, but without PKE or PUE, which means that no pull was actually enabled in the pad. This might be a bug in those boards, but this patch does not change the behavior, so it just removes the meaningless pull value from those definitions. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-28imx: Homogenize and fix fuse register definitionsBenoît Thébaudeau
IIM: - Homogenize prg_p naming (the reference manuals are not always self-consistent for that). - Add missing SCSx and bank registers. - Fix the number of banks on i.MX53. OCOTP: - Rename iim to ocotp in order to avoid confusion. - Rename fuse_data to read_fuse_data, and sticky to sw_sticky, according to the reference manual. - Merge the existing spinoff gp1 fuse definition on i.MX6. - Fix the number of banks on i.MX6. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Stefano Babic <sbabic@denx.de>
2013-04-25mx53ard: Move register masks into imx-regs.hFabio Estevam
imx-regs.h is more appropriate location for containing register masks. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
2013-04-25mx6qsabresd: Return status when initializing MMCOtavio Salvador
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2013-04-25imx: mx6q_4x_mt41j128.cfg: Setup CCM_CCOSR registerFabio Estevam
Setup CCM_CCOSR register to provide a CKO1 clock frequency of 16.5 MHz. CKO1 drives sgtl5000 codec clock on mx6qsabrelite and doing this setup in the bootloader will allow us to remove a lot of code in arch/arm/mach-imx/mach-imx6q.c from the mainline kernel. mx6q_4x_mt41j128.cfg is also used by mx6qsabresd, and it is safe to use it for this board as well. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-22imx: Add titanium board support (i.MX6 based)Stefan Roese
Titanium is a i.MX6 based board from ProjectionDesign / Barco. This patch adds support for this board with the newly introduced NAND support for i.MX6. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-22mx6sl: Add initial support for mx6slevk boardFabio Estevam
mx6slevk board is a development board from Freescale based on the mx6 solo-lite processor. For details about mx6slevk, please refer to: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=IMX6SLEVK&parentCode=i.MX6SL&fpsp=1 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-13ARM: Fix __bss_start and __bss_end in linker scriptsAlbert ARIBAUD
Commit 3ebd1cbc introduced compiler-generated __bss_start and __bss_end__ and commit c23561e7 rewrote all __bss_end__ as __bss_end. Their merge caused silent and harmless but potentially bug-inducing clashes between compiler- and linker- generated __bss_end symbols. Make __bss_end and __bss_start compiler-only, and create __bss_base and __bss_limit for linker-only use. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reported-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12arm: Make all linker scripts compatible with per-symbol sectionsBenoît Thébaudeau
Let all ARM linker scripts handle properly -ffunction-sections and -fdata-sections. This will be useful for future changes in order to create symbol-specific sections in common .S files. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12arm: Remove unused relocate_code() parametersBenoît Thébaudeau
Commit e05e5de7fae5bec79617e113916dac6631251156 made the 2 1st parameters of ARM's relocate_code() useless since it moved the code handling them to crt0.S. So, drop these parameters. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12nand: mxc: Switch NAND SPL to generic SPLBenoît Thébaudeau
This also fixes support for mx31pdk and tx25, which had been broken by commit e05e5de7fae5bec79617e113916dac6631251156. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Scott Wood <scottwood@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-12imx: mx53ard: Add support for NAND FlashBenoît Thébaudeau
Add support for the Samsung K9LAG08U0M NAND Flash (2-GiB MLC NAND Flash, 2-kiB pages, 256-kiB blocks, 30-ns R/W cycles, 1 CS) on mx53ard. eNFC_CLK_ROOT is set up with a cycle time of 37.5 ns (400 MHz / 3 / 5) for this board, which satisfies the 30-ns NF R/W cycle requirement. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-04Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD
2013-04-03i.MX6: mx6qsabrelite: README: don't pass chip-select to sf probe commandJavier Martinez Canillas
board/freescale/mx6qsabrelite/README explain a procedure to update the SPI-NOR on the SabreLite board without Freescale manufacturing tool but following this procedure leads to both "sf erase" and "sf write" failing on a mx6qsabrelite board: MX6QSABRELITE U-Boot > sf probe 1 MX6QSABRELITE U-Boot > sf erase 0 0x40000 SPI flash erase failed MX6QSABRELITE U-Boot > sf write 0x10800000 0 0x40000 SPI flash write failed This is because the chip-select 1 is wrong and the correct value is 0x7300. Since commit c1173bd0 ("sf command: allow default bus and chip selects") the chip-select and bus arguments for the sf probe command are optional so let's just remove it and use "sf probe" instead. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
2013-04-03mx6: Fix get_board_rev() for the mx6 solo caseFabio Estevam
When booting a Freescale kernel 3.0.35 on a Wandboard solo, the get_board_rev() returns 0x62xxx, which is not a value understood by the VPU (Video Processing Unit) library in the kernel and causes the video playback to fail. The expected values for get_board_rev are: 0x63xxx: For mx6quad/dual 0x61xxx: For mx6dual-lite/solo So adjust get_board_rev() accordingly and make it as weak function, so that we do not need to define it in every mx6 board file. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Eric Nelson <eric.nelson@boundarydevices.com>
2013-04-03mmc: i.MX6: fsl_esdhc: Define maximum bus width supported by a boardAbbas Raza
Maximum bus width supported by some i.MX6 boards is not 8bit like others. In case where both host controller and card support 8bit transfers, they agree to communicate on 8bit interface while some boards support only 4bit interface. Due to this reason the mmc 8bit default mode fails on these boards. To rectify this, define maximum bus width supported by these boards (4bit). If max_bus_width is not defined, it is 0 by default and 8bit width support will be enabled in host capabilities otherwise host capabilities are modified accordingly. It is tested with a MMCplus card. Signed-off-by: Abbas Raza <Abbas_Raza@mentor.com> cc: stefano Babic <sbabic@denx.de> cc: Andy Fleming <afleming@gmail.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
2013-04-03mx6qsabrelite: README: No need to pass 'u-boot.imx'Fabio Estevam
The u-boot.imx binary is generated by default, so no need to pass it in the 'make' line. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
generated by cgit (git 2.34.1) at 2024-12-26 14:17:50 +0000